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[PATCH v13 13/24] hw/intc/arm_gicv3: Add has-nmi property to GICv3 devic
From: |
Jinjie Ruan |
Subject: |
[PATCH v13 13/24] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device |
Date: |
Sun, 7 Apr 2024 08:17:22 +0000 |
Add a property has-nmi to the GICv3 device, and use this to set
the NMI bit in the GICD_TYPER register. This isn't visible to
guests yet because the property defaults to false and we won't
set it in the board code until we've landed all of the changes
needed to implement FEAT_GICV3_NMI.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
v12:
- Update the subject and commit message.
- Add Reviewed-by.
v10:
- Adjust to before add irq non-maskable property.
v4:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_dist.c | 2 ++
hw/intc/gicv3_internal.h | 1 +
include/hw/intc/arm_gicv3_common.h | 1 +
4 files changed, 5 insertions(+)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index c52f060026..2d2cea6858 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -569,6 +569,7 @@ static Property arm_gicv3_common_properties[] = {
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
+ DEFINE_PROP_BOOL("has-nmi", GICv3State, nmi_support, 0),
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
/*
* Compatibility property: force 8 bits of physical priority, even
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index 35e850685c..22ddc0d666 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -389,6 +389,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
* by GICD_TYPER.IDbits)
* MBIS == 0 (message-based SPIs not supported)
* SecurityExtn == 1 if security extns supported
+ * NMI = 1 if Non-maskable interrupt property is supported
* CPUNumber == 0 since for us ARE is always 1
* ITLinesNumber == (((max SPI IntID + 1) / 32) - 1)
*/
@@ -402,6 +403,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
bool dvis = s->revision >= 4;
*data = (1 << 25) | (1 << 24) | (dvis << 18) | (sec_extn << 10) |
+ (s->nmi_support << GICD_TYPER_NMI_SHIFT) |
(s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
(0xf << 19) | itlinesnumber;
return true;
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 29d5cdc1b6..8f4ebed2f4 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -68,6 +68,7 @@
#define GICD_CTLR_E1NWF (1U << 7)
#define GICD_CTLR_RWP (1U << 31)
+#define GICD_TYPER_NMI_SHIFT 9
#define GICD_TYPER_LPIS_SHIFT 17
/* 16 bits EventId */
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/intc/arm_gicv3_common.h
index 7324c7d983..4358c5319c 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -249,6 +249,7 @@ struct GICv3State {
uint32_t num_irq;
uint32_t revision;
bool lpi_enable;
+ bool nmi_support;
bool security_extn;
bool force_8bit_prio;
bool irq_reset_nonsecure;
--
2.34.1
- [PATCH v13 02/24] target/arm: Add PSTATE.ALLINT, (continued)
- [PATCH v13 02/24] target/arm: Add PSTATE.ALLINT, Jinjie Ruan, 2024/04/07
- [PATCH v13 01/24] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI, Jinjie Ruan, 2024/04/07
- [PATCH v13 04/24] target/arm: Implement ALLINT MSR (immediate), Jinjie Ruan, 2024/04/07
- [PATCH v13 03/24] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Jinjie Ruan, 2024/04/07
- [PATCH v13 05/24] target/arm: Support MSR access to ALLINT, Jinjie Ruan, 2024/04/07
- [PATCH v13 08/24] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI, Jinjie Ruan, 2024/04/07
- [PATCH v13 07/24] target/arm: Add support for NMI in arm_phys_excp_target_el(), Jinjie Ruan, 2024/04/07
- [PATCH v13 06/24] target/arm: Add support for Non-maskable Interrupt, Jinjie Ruan, 2024/04/07
- [PATCH v13 09/24] target/arm: Handle PSTATE.ALLINT on taking an exception, Jinjie Ruan, 2024/04/07
- [PATCH v13 10/24] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/04/07
- [PATCH v13 13/24] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device,
Jinjie Ruan <=
- [PATCH v13 14/24] hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3, Jinjie Ruan, 2024/04/07
- [PATCH v13 22/24] hw/intc/arm_gicv3: Report the VINMI interrupt, Jinjie Ruan, 2024/04/07
- [PATCH v13 20/24] hw/intc/arm_gicv3: Implement NMI interrupt priority, Jinjie Ruan, 2024/04/07
- [PATCH v13 11/24] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, Jinjie Ruan, 2024/04/07
- [PATCH v13 21/24] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(), Jinjie Ruan, 2024/04/07
- [PATCH v13 15/24] hw/intc/arm_gicv3: Add irq non-maskable property, Jinjie Ruan, 2024/04/07
- [PATCH v13 12/24] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Jinjie Ruan, 2024/04/07
- [PATCH v13 23/24] target/arm: Add FEAT_NMI to max, Jinjie Ruan, 2024/04/07
- [PATCH v13 16/24] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Jinjie Ruan, 2024/04/07
- [PATCH v13 18/24] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Jinjie Ruan, 2024/04/07