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[PULL 10/28] target/mips: Convert Vr54xx MACC* opcodes to decodetree
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 10/28] target/mips: Convert Vr54xx MACC* opcodes to decodetree |
Date: |
Wed, 25 Aug 2021 15:01:53 +0200 |
Convert the following Integer Multiply-Accumulate opcodes:
* MACC Multiply, accumulate, and move LO
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCU Unsigned multiply, accumulate, and move LO
Since all opcodes are generated using the same pattern, we
add the gen_helper_mult_acc_t typedef and MULT_ACC() macro
to remove boilerplate code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-6-f4bug@amsat.org>
---
target/mips/tcg/vr54xx.decode | 9 ++++++++
target/mips/tcg/translate.c | 16 ---------------
target/mips/tcg/vr54xx_translate.c | 33 ++++++++++++++++++++++++++++++
3 files changed, 42 insertions(+), 16 deletions(-)
diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode
index f6b3e42c999..73778f101a5 100644
--- a/target/mips/tcg/vr54xx.decode
+++ b/target/mips/tcg/vr54xx.decode
@@ -6,3 +6,12 @@
#
# Reference: VR5432 Microprocessor User’s Manual
# (Document Number U13751EU5V0UM00)
+
+&r rs rt rd
+
+@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r
+
+MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd
+MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd
+MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd
+MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 34363639937..fd8ffadf06e 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -300,16 +300,12 @@ enum {
enum {
OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
- OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
- OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
- OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
- OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
};
@@ -3780,12 +3776,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t
opc,
case OPC_VR54XX_MULSU:
gen_helper_mulsu(t0, cpu_env, t0, t1);
break;
- case OPC_VR54XX_MACC:
- gen_helper_macc(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MACCU:
- gen_helper_maccu(t0, cpu_env, t0, t1);
- break;
case OPC_VR54XX_MSAC:
gen_helper_msac(t0, cpu_env, t0, t1);
break;
@@ -3804,12 +3794,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t
opc,
case OPC_VR54XX_MULSHIU:
gen_helper_mulshiu(t0, cpu_env, t0, t1);
break;
- case OPC_VR54XX_MACCHI:
- gen_helper_macchi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MACCHIU:
- gen_helper_macchiu(t0, cpu_env, t0, t1);
- break;
case OPC_VR54XX_MSACHI:
gen_helper_msachi(t0, cpu_env, t0, t1);
break;
diff --git a/target/mips/tcg/vr54xx_translate.c
b/target/mips/tcg/vr54xx_translate.c
index 13e58fdd8df..0e2d460c985 100644
--- a/target/mips/tcg/vr54xx_translate.c
+++ b/target/mips/tcg/vr54xx_translate.c
@@ -17,3 +17,36 @@
/* Include the auto-generated decoder. */
#include "decode-vr54xx.c.inc"
+
+/*
+ * Integer Multiply-Accumulate Instructions
+ *
+ * MACC Multiply, accumulate, and move LO
+ * MACCHI Multiply, accumulate, and move HI
+ * MACCHIU Unsigned multiply, accumulate, and move HI
+ * MACCU Unsigned multiply, accumulate, and move LO
+ */
+
+static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
+ void (*gen_helper_mult_acc)(TCGv, TCGv_ptr, TCGv,
TCGv))
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, a->rs);
+ gen_load_gpr(t1, a->rt);
+
+ gen_helper_mult_acc(t0, cpu_env, t0, t1);
+
+ gen_store_gpr(t0, a->rd);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return false;
+}
+
+TRANS(MACC, trans_mult_acc, gen_helper_macc);
+TRANS(MACCHI, trans_mult_acc, gen_helper_macchi);
+TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu);
+TRANS(MACCU, trans_mult_acc, gen_helper_maccu);
--
2.31.1
- [PULL 00/28] MIPS patches for 2021-08-25, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 01/28] target/mips: Remove JR opcode unused arguments, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 02/28] target/mips: Simplify PREF opcode, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 03/28] target/mips: Decode vendor extensions before MIPS ISAs, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 04/28] target/mips: Merge 32-bit/64-bit Release6 decodetree definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 06/28] target/mips: Introduce generic TRANS() macro for decodetree helpers, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 05/28] target/mips: Rename 'rtype' as 'r', Philippe Mathieu-Daudé, 2021/08/25
- [PULL 07/28] target/mips: Extract NEC Vr54xx helper definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 08/28] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 09/28] target/mips: Introduce decodetree structure for NEC Vr54xx extension, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 10/28] target/mips: Convert Vr54xx MACC* opcodes to decodetree,
Philippe Mathieu-Daudé <=
- [PULL 11/28] target/mips: Convert Vr54xx MUL* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 12/28] target/mips: Convert Vr54xx MSA* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 13/28] target/mips: Document Loongson-3A CPU definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 15/28] target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 16/28] target/mips: Remove gen_helper_0e3i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 17/28] target/mips: Remove gen_helper_1e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 19/28] target/mips: Simplify gen_helper() macros by using tcg_constant_i32(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 20/28] target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros, Philippe Mathieu-Daudé, 2021/08/25