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[PULL 14/30] target/arm: Fix fault reporting in get_phys_addr_lpae
From: |
Peter Maydell |
Subject: |
[PULL 14/30] target/arm: Fix fault reporting in get_phys_addr_lpae |
Date: |
Tue, 25 Oct 2022 17:39:36 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Always overriding fi->type was incorrect, as we would not properly
propagate the fault type from S1_ptw_translate, or arm_ldq_ptw.
Simplify things by providing a new label for a translation fault.
For other faults, store into fi directly.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20221024051851.3074715-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 31 +++++++++++++------------------
1 file changed, 13 insertions(+), 18 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 2a5f0188357..3302376e42e 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1044,8 +1044,6 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
ARMCPU *cpu = env_archcpu(env);
ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
bool is_secure = ptw->in_secure;
- /* Read an LPAE long-descriptor translation table. */
- ARMFaultType fault_type = ARMFault_Translation;
uint32_t level;
ARMVAParameters param;
uint64_t ttbr;
@@ -1082,8 +1080,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
* so our choice is to always raise the fault.
*/
if (param.tsz_oob) {
- fault_type = ARMFault_Translation;
- goto do_fault;
+ goto do_translation_fault;
}
addrsize = 64 - 8 * param.tbi;
@@ -1120,8 +1117,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
addrsize - inputsize);
if (-top_bits != param.select) {
/* The gap between the two regions is a Translation fault */
- fault_type = ARMFault_Translation;
- goto do_fault;
+ goto do_translation_fault;
}
}
@@ -1147,7 +1143,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
* Translation table walk disabled => Translation fault on TLB miss
* Note: This is always 0 on 64-bit EL2 and EL3.
*/
- goto do_fault;
+ goto do_translation_fault;
}
if (!regime_is_stage2(mmu_idx)) {
@@ -1178,8 +1174,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
if (param.ds && stride == 9 && sl2) {
if (sl0 != 0) {
level = 0;
- fault_type = ARMFault_Translation;
- goto do_fault;
+ goto do_translation_fault;
}
startlevel = -1;
} else if (!aarch64 || stride == 9) {
@@ -1198,8 +1193,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
inputsize, stride, outputsize);
if (!ok) {
- fault_type = ARMFault_Translation;
- goto do_fault;
+ goto do_translation_fault;
}
level = startlevel;
}
@@ -1221,7 +1215,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
descaddr |= extract64(ttbr, 2, 4) << 48;
} else if (descaddr >> outputsize) {
level = 0;
- fault_type = ARMFault_AddressSize;
+ fi->type = ARMFault_AddressSize;
goto do_fault;
}
@@ -1282,7 +1276,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) {
/* Invalid, or the Reserved level 3 encoding */
- goto do_fault;
+ goto do_translation_fault;
}
descaddr = descriptor & descaddrmask;
@@ -1300,7 +1294,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
descaddr |= extract64(descriptor, 12, 4) << 48;
}
} else if (descaddr >> outputsize) {
- fault_type = ARMFault_AddressSize;
+ fi->type = ARMFault_AddressSize;
goto do_fault;
}
@@ -1357,9 +1351,9 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
* Here descaddr is the final physical address, and attributes
* are all in attrs.
*/
- fault_type = ARMFault_AccessFlag;
if ((attrs & (1 << 8)) == 0) {
/* Access flag */
+ fi->type = ARMFault_AccessFlag;
goto do_fault;
}
@@ -1376,8 +1370,8 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
}
- fault_type = ARMFault_Permission;
if (!(result->f.prot & (1 << access_type))) {
+ fi->type = ARMFault_Permission;
goto do_fault;
}
@@ -1422,8 +1416,9 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
result->f.lg_page_size = ctz64(page_size);
return false;
-do_fault:
- fi->type = fault_type;
+ do_translation_fault:
+ fi->type = ARMFault_Translation;
+ do_fault:
fi->level = level;
/* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
fi->stage2 = fi->s1ptw || regime_is_stage2(mmu_idx);
--
2.25.1
- [PULL 02/30] hw/arm/virt: Fix devicetree warnings about the virtio-iommu node, (continued)
- [PULL 02/30] hw/arm/virt: Fix devicetree warnings about the virtio-iommu node, Peter Maydell, 2022/10/25
- [PULL 06/30] target/imx: reload cmp timer outside of the reload ptimer transaction, Peter Maydell, 2022/10/25
- [PULL 09/30] target/arm: Add isar predicates for FEAT_HAFDBS, Peter Maydell, 2022/10/25
- [PULL 08/30] target/arm: Add ptw_idx to S1Translate, Peter Maydell, 2022/10/25
- [PULL 04/30] hw/core/resettable: fix reset level counting, Peter Maydell, 2022/10/25
- [PULL 03/30] target/arm: honor HCR_E2H and HCR_TGE in arm_excp_unmasked(), Peter Maydell, 2022/10/25
- [PULL 10/30] target/arm: Extract HA and HD in aa64_va_parameters, Peter Maydell, 2022/10/25
- [PULL 11/30] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, Peter Maydell, 2022/10/25
- [PULL 15/30] target/arm: Don't shift attrs in get_phys_addr_lpae, Peter Maydell, 2022/10/25
- [PULL 16/30] target/arm: Consider GP an attribute in get_phys_addr_lpae, Peter Maydell, 2022/10/25
- [PULL 14/30] target/arm: Fix fault reporting in get_phys_addr_lpae,
Peter Maydell <=
- [PULL 17/30] target/arm: Tidy merging of attributes from descriptor and table, Peter Maydell, 2022/10/25
- [PULL 12/30] target/arm: Add ARMFault_UnsuppAtomicUpdate, Peter Maydell, 2022/10/25
- [PULL 13/30] target/arm: Remove loop from get_phys_addr_lpae, Peter Maydell, 2022/10/25
- [PULL 18/30] target/arm: Implement FEAT_HAFDBS, access flag portion, Peter Maydell, 2022/10/25
- [PULL 19/30] target/arm: Implement FEAT_HAFDBS, dirty bit portion, Peter Maydell, 2022/10/25
- [PULL 07/30] target/arm: Introduce regime_is_stage2, Peter Maydell, 2022/10/25
- [PULL 21/30] reset: allow registering handlers that aren't called by snapshot loading, Peter Maydell, 2022/10/25
- [PULL 23/30] x86: do not re-randomize RNG seed on snapshot load, Peter Maydell, 2022/10/25
- [PULL 28/30] mips/boston: re-randomize rng-seed on reboot, Peter Maydell, 2022/10/25
- [PULL 30/30] rx: re-randomize rng-seed on reboot, Peter Maydell, 2022/10/25