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Re: [PATCH 05/11] tcg/riscv: Use ADD.UW for guest address generation
From: |
Alistair Francis |
Subject: |
Re: [PATCH 05/11] tcg/riscv: Use ADD.UW for guest address generation |
Date: |
Wed, 17 May 2023 09:43:24 +1000 |
On Wed, May 3, 2023 at 6:58 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The instruction is a combined zero-extend and add.
> Use it for exactly that.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tcg/riscv/tcg-target.c.inc | 33 ++++++++++++++++++++++-----------
> 1 file changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 53a7f97b29..f64eaa8515 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1039,14 +1039,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext
> *s, TCGReg *pbase,
> tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
>
> /* TLB Hit - translate address using addend. */
> - addr_adj = addr_reg;
> - if (TARGET_LONG_BITS == 32) {
> - addr_adj = TCG_REG_TMP0;
> - tcg_out_ext32u(s, addr_adj, addr_reg);
> + if (TARGET_LONG_BITS == 64) {
> + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
> + } else if (have_zba) {
> + tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
> + } else {
> + tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
> + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0,
> TCG_REG_TMP2);
> }
> - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_adj);
> *pbase = TCG_REG_TMP0;
> #else
> + TCGReg base;
> +
> if (a_mask) {
> ldst = new_ldst_label(s);
> ldst->is_ld = is_ld;
> @@ -1061,14 +1065,21 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext
> *s, TCGReg *pbase,
> tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0);
> }
>
> - TCGReg base = addr_reg;
> - if (TARGET_LONG_BITS == 32) {
> - tcg_out_ext32u(s, TCG_REG_TMP0, base);
> - base = TCG_REG_TMP0;
> - }
> if (guest_base != 0) {
> - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
> base = TCG_REG_TMP0;
> + if (TARGET_LONG_BITS == 64) {
> + tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG);
> + } else if (have_zba) {
> + tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg,
> TCG_GUEST_BASE_REG);
> + } else {
> + tcg_out_ext32u(s, base, addr_reg);
> + tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG);
> + }
> + } else if (TARGET_LONG_BITS == 64) {
> + base = addr_reg;
> + } else {
> + base = TCG_REG_TMP0;
> + tcg_out_ext32u(s, base, addr_reg);
> }
> *pbase = base;
> #endif
> --
> 2.34.1
>
>
- Re: [PATCH 01/11] disas/riscv: Decode czero.{eqz,nez}, (continued)
- [PATCH 02/11] tcg/riscv: Probe for Zba, Zbb, Zicond extensions, Richard Henderson, 2023/05/03
- [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Richard Henderson, 2023/05/03
- Re: [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Daniel Henrique Barboza, 2023/05/08
- Re: [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Alistair Francis, 2023/05/16
- [PATCH 05/11] tcg/riscv: Use ADD.UW for guest address generation, Richard Henderson, 2023/05/03
- [PATCH 07/11] tcg/riscv: Support REV8 from Zbb, Richard Henderson, 2023/05/03
- [PATCH 09/11] tcg/riscv: Improve setcond expansion, Richard Henderson, 2023/05/03
- [PATCH 10/11] tcg/riscv: Implement movcond, Richard Henderson, 2023/05/03
- [PATCH 08/11] tcg/riscv: Support CPOP from Zbb, Richard Henderson, 2023/05/03