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[PATCH v2 06/20] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G
From: |
Richard Henderson |
Subject: |
[PATCH v2 06/20] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G |
Date: |
Thu, 25 May 2023 16:25:44 -0700 |
This fixes a bug in that these two insns should have been using atomic
16-byte stores, since MTE is ARMv8.5 and LSE2 is mandatory from ARMv8.4.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 6bb68618a0..51f9d227e7 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -4070,15 +4070,18 @@ static void disas_ldst_tag(DisasContext *s, uint32_t
insn)
if (is_zero) {
TCGv_i64 clean_addr = clean_data_tbi(s, addr);
- TCGv_i64 tcg_zero = tcg_constant_i64(0);
+ TCGv_i64 zero64 = tcg_constant_i64(0);
+ TCGv_i128 zero128 = tcg_temp_new_i128();
int mem_index = get_mem_index(s);
- int i, n = (1 + is_pair) << LOG2_TAG_GRANULE;
+ MemOp mop = finalize_memop(s, MO_128 | MO_ALIGN);
- tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index,
- MO_UQ | MO_ALIGN_16);
- for (i = 8; i < n; i += 8) {
- tcg_gen_addi_i64(clean_addr, clean_addr, 8);
- tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ);
+ tcg_gen_concat_i64_i128(zero128, zero64, zero64);
+
+ /* This is 1 or 2 atomic 16-byte operations. */
+ tcg_gen_qemu_st_i128(zero128, clean_addr, mem_index, mop);
+ if (is_pair) {
+ tcg_gen_addi_i64(clean_addr, clean_addr, 16);
+ tcg_gen_qemu_st_i128(zero128, clean_addr, mem_index, mop);
}
}
--
2.34.1
- [PATCH v2 00/20] target/arm: Implement FEAT_LSE2, Richard Henderson, 2023/05/25
- [PATCH v2 04/20] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP, Richard Henderson, 2023/05/25
- [PATCH v2 08/20] target/arm: Sink gen_mte_check1 into load/store_exclusive, Richard Henderson, 2023/05/25
- [PATCH v2 02/20] target/arm: Add feature test for FEAT_LSE2, Richard Henderson, 2023/05/25
- [PATCH v2 06/20] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G,
Richard Henderson <=
- [PATCH v2 09/20] target/arm: Load/store integer pair with one tcg operation, Richard Henderson, 2023/05/25
- [PATCH v2 10/20] target/arm: Hoist finalize_memop out of do_gpr_{ld, st}, Richard Henderson, 2023/05/25
- [PATCH v2 14/20] target/arm: Check alignment in helper_mte_check, Richard Henderson, 2023/05/25
- [PATCH v2 12/20] target/arm: Pass memop to gen_mte_check1*, Richard Henderson, 2023/05/25
- [PATCH v2 15/20] target/arm: Add SCTLR.nAA to TBFLAG_A64, Richard Henderson, 2023/05/25
- [PATCH v2 19/20] tests/tcg/multiarch: Adjust sigbus.c, Richard Henderson, 2023/05/25
- [PATCH v2 01/20] target/arm: Add commentary for CPUARMState.exclusive_high, Richard Henderson, 2023/05/25