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[PATCH] i386/cpu: Don't emulate L3 cache on 8000_001D if l3-cache is dis


From: Yanan Wang
Subject: [PATCH] i386/cpu: Don't emulate L3 cache on 8000_001D if l3-cache is disabled
Date: Wed, 31 May 2023 20:00:28 +0800

Currently, we only avoid emulating L3 cache properties for AMD CPU
when l3-cache is off, but failed to consider this case on CPUID 8000_001D.
This result in a fact that we will still have L3 caches in the VM
although we pass "host-cache-info=off,l3-cache=off" CLI to qemu.

Fixes: 8f4202fb108 ("i386: Populate AMD Processor Cache Information for cpuid 
0x8000001D")
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
---
 target/i386/cpu.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1242bd541a..17c367c5ba 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6337,8 +6337,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, 
uint32_t count,
                                        &topo_info, eax, ebx, ecx, edx);
             break;
         case 3: /* L3 cache info */
-            encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
-                                       &topo_info, eax, ebx, ecx, edx);
+            if (cpu->enable_l3_cache) {
+                encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
+                                           &topo_info, eax, ebx, ecx, edx);
+            }
             break;
         default: /* end of info */
             *eax = *ebx = *ecx = *edx = 0;
-- 
2.33.0




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