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[PATCH 45/85] target/sparc: Move LDSTUB, LDSTUBA to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH 45/85] target/sparc: Move LDSTUB, LDSTUBA to decodetree |
Date: |
Fri, 13 Oct 2023 14:28:06 -0700 |
Remove gen_ldstub_asi.
Rename gen_ldstub_asi0 to gen_ldstub_asi.
Merge gen_ldstub into gen_ldstub_asi.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 4 ++++
target/sparc/translate.c | 46 +++++++++++++++++++--------------------
2 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index fd9e268a0e..0d3bb3b588 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -278,6 +278,10 @@ STD 11 ..... 010111 ..... . .............
@r_r_i_asi # STDA
STX 11 ..... 011110 ..... . ............. @r_r_r_asi # STXA
STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA
+LDSTUB 11 ..... 001101 ..... . ............. @r_r_ri_na
+LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LDSTUBA
+LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LDSTUBA
+
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 11f885822f..052000e4f7 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1800,13 +1800,6 @@ static void gen_swap(DisasContext *dc, TCGv dst, TCGv
src,
tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN);
}
-static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
-{
- TCGv m1 = tcg_constant_tl(0xff);
- gen_address_mask(dc, addr);
- tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB);
-}
-
/* asi moves */
typedef enum {
GET_ASI_HELPER,
@@ -2225,13 +2218,14 @@ gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
int insn, int rd)
gen_store_gpr(dc, rd, oldv);
}
-static void gen_ldstub_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv
addr)
+static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
{
switch (da->type) {
case GET_ASI_EXCP:
break;
case GET_ASI_DIRECT:
- gen_ldstub(dc, dst, addr, da->mem_idx);
+ tcg_gen_atomic_xchg_tl(dst, addr, tcg_constant_tl(0xff),
+ da->mem_idx, MO_UB);
break;
default:
/* ??? In theory, this should be raise DAE_invalid_asi.
@@ -2259,15 +2253,6 @@ static void gen_ldstub_asi0(DisasContext *dc, DisasASI
*da, TCGv dst, TCGv addr)
}
}
-static void __attribute__((unused))
-gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
-{
- DisasASI da = get_asi(dc, insn, MO_UB);
-
- gen_address_mask(dc, addr);
- gen_ldstub_asi0(dc, &da, dst, addr);
-}
-
static void __attribute__((unused))
gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
{
@@ -4623,6 +4608,23 @@ static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi
*a)
return advance_pc(dc);
}
+static bool trans_LDSTUB(DisasContext *dc, arg_r_r_ri_asi *a)
+{
+ TCGv addr, reg;
+ DisasASI da;
+
+ addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
+ if (addr == NULL) {
+ return false;
+ }
+ da = resolve_asi(dc, a->asi, MO_UB);
+
+ reg = gen_dest_gpr(dc, a->rd);
+ gen_ldstub_asi(dc, &da, reg, addr);
+ gen_store_gpr(dc, a->rd, reg);
+ return advance_pc(dc);
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -5451,21 +5453,20 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
case 0x3: /* ldd, load double word */
case 0x9: /* ldsb, load signed byte */
case 0xa: /* ldsh, load signed halfword */
+ case 0xd: /* ldstub */
case 0x10: /* lda, V9 lduwa, load word alternate */
case 0x11: /* lduba, load unsigned byte alternate */
case 0x12: /* lduha, load unsigned halfword alternate */
case 0x13: /* ldda, load double word alternate */
case 0x19: /* ldsba, load signed byte alternate */
case 0x1a: /* ldsha, load signed halfword alternate */
+ case 0x1d: /* ldstuba */
g_assert_not_reached(); /* in decodetree */
case 0x08: /* V9 ldsw */
case 0x0b: /* V9 ldx */
case 0x18: /* V9 ldswa */
case 0x1b: /* V9 ldxa */
goto illegal_insn; /* in decodetree */
- case 0xd: /* ldstub */
- gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
- break;
case 0x0f:
/* swap, swap register with memory. Also atomically */
cpu_src1 = gen_load_gpr(dc, rd);
@@ -5473,9 +5474,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned
int insn)
dc->mem_idx, MO_TEUL);
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- case 0x1d: /* ldstuba -- XXX: should be atomically */
- gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
- break;
case 0x1f: /* swapa, swap reg with alt. memory. Also
atomically */
cpu_src1 = gen_load_gpr(dc, rd);
--
2.34.1
- [PATCH 33/85] target/sparc: Move MOVcc, MOVR to decodetree, (continued)
- [PATCH 33/85] target/sparc: Move MOVcc, MOVR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 37/85] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree, Richard Henderson, 2023/10/13
- [PATCH 36/85] target/sparc: Move JMPL, RETT, RETURN to decodetree, Richard Henderson, 2023/10/13
- [PATCH 38/85] target/sparc: Move DONE, RETRY to decodetree, Richard Henderson, 2023/10/13
- [PATCH 39/85] target/sparc: Split out resolve_asi, Richard Henderson, 2023/10/13
- [PATCH 42/85] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX, Richard Henderson, 2023/10/13
- [PATCH 44/85] target/sparc: Move asi integer load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 41/85] target/sparc: Split out ldst functions with asi pre-computed, Richard Henderson, 2023/10/13
- [PATCH 40/85] target/sparc: Drop ifdef around get_asi and friends, Richard Henderson, 2023/10/13
- [PATCH 43/85] target/sparc: Move simple integer load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 45/85] target/sparc: Move LDSTUB, LDSTUBA to decodetree,
Richard Henderson <=
- [PATCH 46/85] target/sparc: Move SWAP, SWAPA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 51/85] target/sparc: Move asi fp load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 50/85] target/sparc: Move simple fp load/store to decodetree, Richard Henderson, 2023/10/13
- [PATCH 47/85] target/sparc: Move CASA, CASXA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 52/85] target/sparc: Move LDFSR, STFSR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations, Richard Henderson, 2023/10/13
- [PATCH 54/85] target/sparc: Move EDGE* to decodetree, Richard Henderson, 2023/10/13
- [PATCH 56/85] target/sparc: Move ADDRALIGN* to decodetree, Richard Henderson, 2023/10/13
- [PATCH 57/85] target/sparc: Move BMASK to decodetree, Richard Henderson, 2023/10/13