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[PATCH 39/61] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA
From: |
Richard Henderson |
Subject: |
[PATCH 39/61] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA |
Date: |
Wed, 18 Oct 2023 14:51:13 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 15 +++++++++++----
target/hppa/translate.c | 4 ++++
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 48f09c9b06..33eec3f4c3 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -215,9 +215,14 @@ ld 000011 ..... ..... .. . 0 -- 00 size:2
...... @ldstx
st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5
ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2
ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2
+ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3
+ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3
lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2
lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
+lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3
+lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3
sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
+sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3
stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \
@@ -244,6 +249,8 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . .....
@fldstdi
# Offset Mem
####
+@ldstim11 ...... b:5 t:5 sp:2 .............. \
+ &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
@ldstim14 ...... b:5 t:5 sp:2 .............. \
&ldst disp=%lowsign_14 x=0 scale=0 m=0
@ldstim14m ...... b:5 t:5 sp:2 .............. \
@@ -275,11 +282,11 @@ fstw 011110 b:5 ..... sp:2 .............. \
fstw 011111 b:5 ..... sp:2 ...........0.. \
&ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
-fldd 010100 b:5 t:5 sp:2 .......... .. 1 . \
- &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
+ld 010100 ..... ..... .. ............0. @ldstim11
+fldd 010100 ..... ..... .. ............1. @ldstim11
-fstd 011100 b:5 t:5 sp:2 .......... .. 1 . \
- &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
+st 011100 ..... ..... .. ............0. @ldstim11
+fstd 011100 ..... ..... .. ............1. @ldstim11
####
# Floating-point Multiply Add
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 7e723dcd24..308b8dd263 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2951,6 +2951,10 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
TCGv_reg zero, dest, ofs;
TCGv_tl addr;
+ if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
+ return gen_illegal(ctx);
+ }
+
nullify_over(ctx);
if (a->m) {
--
2.34.1
- [PATCH 16/61] target/hppa: Update cpu_hppa_get/put_psw for hppa64, (continued)
- [PATCH 16/61] target/hppa: Update cpu_hppa_get/put_psw for hppa64, Richard Henderson, 2023/10/18
- [PATCH 22/61] target/hppa: Pass d to do_cond, Richard Henderson, 2023/10/18
- [PATCH 23/61] target/hppa: Pass d to do_sub_cond, Richard Henderson, 2023/10/18
- [PATCH 24/61] target/hppa: Pass d to do_log_cond, Richard Henderson, 2023/10/18
- [PATCH 10/61] target/hppa: Fix bb_sar for hppa64, Richard Henderson, 2023/10/18
- [PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU, Richard Henderson, 2023/10/18
- [PATCH 26/61] target/hppa: Pass d to do_unit_cond, Richard Henderson, 2023/10/18
- [PATCH 33/61] target/hppa: Decode d for add instructions, Richard Henderson, 2023/10/18
- [PATCH 32/61] target/hppa: Decode d for cmpclr instructions, Richard Henderson, 2023/10/18
- [PATCH 35/61] target/hppa: Decode d for bb instructions, Richard Henderson, 2023/10/18
- [PATCH 39/61] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA,
Richard Henderson <=
- [PATCH 40/61] target/hppa: Implement DEPD, DEPDI, Richard Henderson, 2023/10/18
- [PATCH 41/61] target/hppa: Implement EXTRD, Richard Henderson, 2023/10/18
- [PATCH 44/61] target/hppa: Implement STDBY, Richard Henderson, 2023/10/18
- [PATCH 43/61] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM, Richard Henderson, 2023/10/18
- [PATCH 45/61] target/hppa: Implement IDTLBT, IITLBT, Richard Henderson, 2023/10/18
- [PATCH 42/61] target/hppa: Implement SHRPD, Richard Henderson, 2023/10/18
- [PATCH 46/61] target/hppa: Remove TARGET_REGISTER_BITS, Richard Henderson, 2023/10/18
- [PATCH 47/61] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections, Richard Henderson, 2023/10/18
- [PATCH 50/61] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64, Richard Henderson, 2023/10/18
- [PATCH 52/61] target/hppa: Implement HSUB, Richard Henderson, 2023/10/18