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[PATCH v2 30/65] target/hppa: Decode d for logical instructions
From: |
Richard Henderson |
Subject: |
[PATCH v2 30/65] target/hppa: Decode d for logical instructions |
Date: |
Fri, 20 Oct 2023 13:42:56 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 10 ++++++----
target/hppa/translate.c | 15 +++++++--------
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index aebe03ccfd..26ca9f1063 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -61,6 +61,7 @@
&rr_cf t r cf
&rrr_cf t r1 r2 cf
+&rrr_cf_d t r1 r2 cf d
&rrr_cf_sh t r1 r2 cf sh
&rri_cf t r i cf
@@ -73,6 +74,7 @@
@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf
@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
+@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0
@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
@@ -150,10 +152,10 @@ lci 000001 ----- ----- -- 01001100 0 t:5
# Arith/Log
####
-andcm 000010 ..... ..... .... 000000 - ..... @rrr_cf
-and 000010 ..... ..... .... 001000 - ..... @rrr_cf
-or 000010 ..... ..... .... 001001 - ..... @rrr_cf
-xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf
+andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d
+and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d
+or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d
+xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d
uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf
ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 450f64bac3..733d5fe067 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1392,11 +1392,10 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,
TCGv_reg in1,
}
static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1,
- TCGv_reg in2, unsigned cf,
+ TCGv_reg in2, unsigned cf, bool d,
void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
{
TCGv_reg dest = dest_gpr(ctx, rt);
- bool d = false;
/* Perform the operation, and writeback. */
fn(dest, in1, in2);
@@ -1409,7 +1408,7 @@ static void do_log(DisasContext *ctx, unsigned rt,
TCGv_reg in1,
}
}
-static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a,
+static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a,
void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
{
TCGv_reg tcg_r1, tcg_r2;
@@ -1419,7 +1418,7 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a,
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
- do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn);
+ do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn);
return nullify_end(ctx);
}
@@ -2672,17 +2671,17 @@ static bool trans_sub_b_tsv(DisasContext *ctx,
arg_rrr_cf *a)
return do_sub_reg(ctx, a, true, true, false);
}
-static bool trans_andcm(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_log_reg(ctx, a, tcg_gen_andc_reg);
}
-static bool trans_and(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_log_reg(ctx, a, tcg_gen_and_reg);
}
-static bool trans_or(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a)
{
if (a->cf == 0) {
unsigned r2 = a->r2;
@@ -2734,7 +2733,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a)
return do_log_reg(ctx, a, tcg_gen_or_reg);
}
-static bool trans_xor(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_log_reg(ctx, a, tcg_gen_xor_reg);
}
--
2.34.1
- [PATCH v2 17/65] target/hppa: Update cpu_hppa_get/put_psw for hppa64, (continued)
- [PATCH v2 17/65] target/hppa: Update cpu_hppa_get/put_psw for hppa64, Richard Henderson, 2023/10/20
- [PATCH v2 15/65] target/hppa: Implement cpu_list, Richard Henderson, 2023/10/20
- [PATCH v2 18/65] target/hppa: Handle absolute addresses for pa2.0, Richard Henderson, 2023/10/20
- [PATCH v2 07/65] target/hppa: Fix load in do_load_32, Richard Henderson, 2023/10/20
- [PATCH v2 08/65] target/hppa: Truncate rotate count in trans_shrpw_sar, Richard Henderson, 2023/10/20
- [PATCH v2 09/65] target/hppa: Fix trans_ds for hppa64, Richard Henderson, 2023/10/20
- [PATCH v2 12/65] target/hppa: Fix extrw and depw with sar for hppa64, Richard Henderson, 2023/10/20
- [PATCH v2 19/65] target/hppa: Adjust hppa_cpu_dump_state for hppa64, Richard Henderson, 2023/10/20
- [PATCH v2 25/65] target/hppa: Pass d to do_sed_cond, Richard Henderson, 2023/10/20
- [PATCH v2 27/65] linux-user/hppa: Fixes for TARGET_ABI32, Richard Henderson, 2023/10/20
- [PATCH v2 30/65] target/hppa: Decode d for logical instructions,
Richard Henderson <=
- [PATCH v2 28/65] target/hppa: Drop attempted gdbstub support for hppa64, Richard Henderson, 2023/10/20
- [PATCH v2 33/65] target/hppa: Decode d for add instructions, Richard Henderson, 2023/10/20
- [PATCH v2 29/65] target/hppa: Remove TARGET_HPPA64, Richard Henderson, 2023/10/20
- [PATCH v2 06/65] target/hppa: Fix hppa64 case in machine.c, Richard Henderson, 2023/10/20
- [PATCH v2 05/65] target/hppa: Remove load_const, Richard Henderson, 2023/10/20
- [PATCH v2 11/65] target/hppa: Fix bb_sar for hppa64, Richard Henderson, 2023/10/20
- [PATCH v2 14/65] target/hppa: Make HPPA_BTLB_ENTRIES variable, Richard Henderson, 2023/10/20
- [PATCH v2 13/65] target/hppa: Introduce TYPE_HPPA64_CPU, Richard Henderson, 2023/10/20