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[PATCH v4 10/90] target/sparc: Define AM_CHECK for sparc32
From: |
Richard Henderson |
Subject: |
[PATCH v4 10/90] target/sparc: Define AM_CHECK for sparc32 |
Date: |
Sat, 21 Oct 2023 22:59:11 -0700 |
Define as false, which allows some ifdef removal.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 080bc5f8a2..9eb2b7e52f 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -268,20 +268,21 @@ static void gen_move_Q(DisasContext *dc, unsigned int rd,
unsigned int rs)
#endif
#endif
-#ifdef TARGET_SPARC64
-#ifndef TARGET_ABI32
-#define AM_CHECK(dc) ((dc)->address_mask_32bit)
+#if !defined(TARGET_SPARC64)
+# define AM_CHECK(dc) false
+#elif defined(TARGET_ABI32)
+# define AM_CHECK(dc) true
+#elif defined(CONFIG_USER_ONLY)
+# define AM_CHECK(dc) false
#else
-#define AM_CHECK(dc) (1)
-#endif
+# define AM_CHECK(dc) ((dc)->address_mask_32bit)
#endif
static void gen_address_mask(DisasContext *dc, TCGv addr)
{
-#ifdef TARGET_SPARC64
- if (AM_CHECK(dc))
+ if (AM_CHECK(dc)) {
tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
-#endif
+ }
}
static TCGv gen_load_gpr(DisasContext *dc, int reg)
@@ -1366,11 +1367,9 @@ static void do_branch(DisasContext *dc, int32_t offset,
uint32_t insn, int cc)
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
target_ulong target = dc->pc + offset;
-#ifdef TARGET_SPARC64
if (unlikely(AM_CHECK(dc))) {
target &= 0xffffffffULL;
}
-#endif
if (cond == 0x0) {
/* unconditional not taken */
if (a) {
@@ -1406,11 +1405,9 @@ static void do_fbranch(DisasContext *dc, int32_t offset,
uint32_t insn, int cc)
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
target_ulong target = dc->pc + offset;
-#ifdef TARGET_SPARC64
if (unlikely(AM_CHECK(dc))) {
target &= 0xffffffffULL;
}
-#endif
if (cond == 0x0) {
/* unconditional not taken */
if (a) {
--
2.34.1
- [PATCH v4 02/90] target/sparc: Implement check_align inline, (continued)
- [PATCH v4 02/90] target/sparc: Implement check_align inline, Richard Henderson, 2023/10/22
- [PATCH v4 04/90] target/sparc: Set TCG_GUEST_DEFAULT_MO, Richard Henderson, 2023/10/22
- [PATCH v4 01/90] target/sparc: Clear may_lookup for npc == DYNAMIC_PC, Richard Henderson, 2023/10/22
- [PATCH v4 07/90] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties, Richard Henderson, 2023/10/22
- [PATCH v4 05/90] configs: Enable MTTCG for sparc, sparc64, Richard Henderson, 2023/10/22
- [PATCH v4 06/90] target/sparc: Define features via cpu-feature.h.inc, Richard Henderson, 2023/10/22
- [PATCH v4 08/90] target/sparc: Remove sparcv7 cpu features, Richard Henderson, 2023/10/22
- [PATCH v4 09/90] target/sparc: Add decodetree infrastructure, Richard Henderson, 2023/10/22
- [PATCH v4 12/90] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 03/90] target/sparc: Avoid helper_raise_exception in helper_st_asi, Richard Henderson, 2023/10/22
- [PATCH v4 10/90] target/sparc: Define AM_CHECK for sparc32,
Richard Henderson <=
- [PATCH v4 11/90] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 13/90] target/sparc: Move BPr to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 14/90] target/sparc: Move FBPfcc and FBfcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 15/90] target/sparc: Merge gen_cond with only caller, Richard Henderson, 2023/10/22
- [PATCH v4 16/90] target/sparc: Merge gen_fcond with only caller, Richard Henderson, 2023/10/22
- [PATCH v4 19/90] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 18/90] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/22
- [PATCH v4 20/90] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 23/90] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 17/90] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/22