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[PULL 34/65] target/riscv/tcg: add 'zic64b' support
From: |
Alistair Francis |
Subject: |
[PULL 34/65] target/riscv/tcg: add 'zic64b' support |
Date: |
Wed, 10 Jan 2024 18:57:02 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
zic64b is defined in the RVA22U64 profile [1] as a named feature for
"Cache blocks must be 64 bytes in size, naturally aligned in the address
space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64
profile mandates this feature, meaning that applications using this
profile expects 64 bytes cache blocks.
To make the upcoming RVA22U64 implementation complete, we'll zic64b as
a 'named feature', not a regular extension. This means that:
- it won't be exposed to users;
- it won't be written in riscv,isa.
This will be extended to other named extensions in the future, so we're
creating some common boilerplate for them as well.
zic64b is default to 'true' since we're already using 64 bytes blocks.
If any cache block size (cbo{m,p,z}_blocksize) is changed to something
different than 64, zic64b is set to 'false'.
Our profile implementation will then be able to check the current state
of zic64b and take the appropriate action (e.g. throw a warning).
[1] https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles.pdf
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 6 ++++++
target/riscv/tcg/tcg-cpu.c | 26 ++++++++++++++++++++++++++
4 files changed, 34 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2725528bb5..bfa42a0393 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -765,6 +765,7 @@ typedef struct RISCVCPUMultiExtConfig {
extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[];
extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[];
extern Property riscv_cpu_options[];
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 2da8ac9582..350ea44e50 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -117,6 +117,7 @@ struct RISCVCPUConfig {
bool ext_smepmp;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
+ bool zic64b;
uint32_t mvendorid;
uint64_t marchid;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ce0a3ded04..29fdd64298 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1443,6 +1443,12 @@ const RISCVCPUMultiExtConfig
riscv_cpu_experimental_exts[] = {
DEFINE_PROP_END_OF_LIST(),
};
+const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
+ MULTI_EXT_CFG_BOOL("zic64b", zic64b, true),
+
+ DEFINE_PROP_END_OF_LIST(),
+};
+
/* Deprecated entries marked for future removal */
const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index e9f980805e..f12e0620e5 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -114,6 +114,19 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
g_assert_not_reached();
}
+static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset)
+{
+ const RISCVCPUMultiExtConfig *feat;
+
+ for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) {
+ if (feat->offset == ext_offset) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env,
uint32_t ext_offset)
{
@@ -123,6 +136,10 @@ static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env,
return;
}
+ if (cpu_cfg_offset_is_named_feat(ext_offset)) {
+ return;
+ }
+
ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset);
if (env->priv_ver < ext_priv_ver) {
@@ -293,6 +310,13 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU
*cpu)
}
}
+static void riscv_cpu_update_named_features(RISCVCPU *cpu)
+{
+ cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 &&
+ cpu->cfg.cbop_blocksize == 64 &&
+ cpu->cfg.cboz_blocksize == 64;
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
@@ -662,6 +686,8 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error
**errp)
return;
}
+ riscv_cpu_update_named_features(cpu);
+
if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
--
2.43.0
- [PULL 26/65] target/riscv: Add support for Zacas extension, (continued)
- [PULL 26/65] target/riscv: Add support for Zacas extension, Alistair Francis, 2024/01/10
- [PULL 18/65] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT, Alistair Francis, 2024/01/10
- [PULL 27/65] disas/riscv: Add amocas.[w,d,q] instructions, Alistair Francis, 2024/01/10
- [PULL 28/65] docs/system/riscv: document acpi parameter of virt machine, Alistair Francis, 2024/01/10
- [PULL 30/65] target/riscv/tcg: do not use "!generic" CPU checks, Alistair Francis, 2024/01/10
- [PULL 31/65] target/riscv/tcg: update priv_ver on user_set extensions, Alistair Francis, 2024/01/10
- [PULL 32/65] target/riscv: add rv64i CPU, Alistair Francis, 2024/01/10
- [PULL 40/65] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Alistair Francis, 2024/01/10
- [PULL 41/65] target/riscv/tcg: handle profile MISA bits, Alistair Francis, 2024/01/10
- [PULL 33/65] target/riscv: add zicbop extension flag, Alistair Francis, 2024/01/10
- [PULL 34/65] target/riscv/tcg: add 'zic64b' support,
Alistair Francis <=
- [PULL 35/65] riscv-qmp-cmds.c: expose named features in cpu_model_expansion, Alistair Francis, 2024/01/10
- [PULL 37/65] target/riscv/kvm: add 'rva22u64' flag as unavailable, Alistair Francis, 2024/01/10
- [PULL 29/65] target/riscv: create TYPE_RISCV_VENDOR_CPU, Alistair Francis, 2024/01/10
- [PULL 36/65] target/riscv: add rva22u64 profile definition, Alistair Francis, 2024/01/10
- [PULL 38/65] target/riscv/tcg: add user flag for profile support, Alistair Francis, 2024/01/10
- [PULL 43/65] target/riscv/tcg: honor user choice for G MISA bits, Alistair Francis, 2024/01/10
- [PULL 39/65] target/riscv/tcg: add MISA user options hash, Alistair Francis, 2024/01/10
- [PULL 42/65] target/riscv/tcg: add hash table insert helpers, Alistair Francis, 2024/01/10
- [PULL 44/65] target/riscv/tcg: validate profiles during finalize, Alistair Francis, 2024/01/10
- [PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion, Alistair Francis, 2024/01/10