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[PULL 52/65] target/riscv: add 'parent' in profile description
From: |
Alistair Francis |
Subject: |
[PULL 52/65] target/riscv: add 'parent' in profile description |
Date: |
Wed, 10 Jan 2024 18:57:20 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Certain S-mode profiles, like RVA22S64 and RVA23S64, mandate all the
mandatory extensions of their respective U-mode profiles. RVA22S64
includes all mandatory extensions of RVA22U64, and the same happens with
RVA23 profiles.
Add a 'parent' field to allow profiles to enable other profiles. This
will allow us to describe S-mode profiles by specifying their parent
U-mode profile, then adding just the S-mode specific extensions.
We're naming the field 'parent' to consider the possibility of other
uses (e.g. a s-mode profile including a previous s-mode profile) in the
future.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-25-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 1 +
target/riscv/tcg/tcg-cpu.c | 14 +++++++++++++-
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 136030434e..5f3955c38d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -77,6 +77,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit);
#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
typedef struct riscv_cpu_profile {
+ struct riscv_cpu_profile *parent;
const char *name;
uint32_t misa_ext;
bool enabled;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1aeb0fee1b..616b091303 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1539,6 +1539,7 @@ Property riscv_cpu_options[] = {
* having a cfg offset) at this moment.
*/
static RISCVCPUProfile RVA22U64 = {
+ .parent = NULL,
.name = "rva22u64",
.misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
.priv_spec = RISCV_PROFILE_ATTR_UNUSED,
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index a0a3350e3e..14133ff665 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -802,7 +802,7 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
CPURISCVState *env = &cpu->env;
const char *warn_msg = "Profile %s mandates disabled extension %s";
bool send_warn = profile->user_set && profile->enabled;
- bool profile_impl = true;
+ bool parent_enabled, profile_impl = true;
int i;
#ifndef CONFIG_USER_ONLY
@@ -855,6 +855,13 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
}
profile->enabled = profile_impl;
+
+ if (profile->parent != NULL) {
+ parent_enabled = object_property_get_bool(OBJECT(cpu),
+ profile->parent->name,
+ NULL);
+ profile->enabled = profile->enabled && parent_enabled;
+ }
}
static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
@@ -1112,6 +1119,11 @@ static void cpu_set_profile(Object *obj, Visitor *v,
const char *name,
profile->user_set = true;
profile->enabled = value;
+ if (profile->parent != NULL) {
+ object_property_set_bool(obj, profile->parent->name,
+ profile->enabled, NULL);
+ }
+
if (profile->enabled) {
cpu->env.priv_ver = profile->priv_spec;
}
--
2.43.0
- [PULL 39/65] target/riscv/tcg: add MISA user options hash, (continued)
- [PULL 39/65] target/riscv/tcg: add MISA user options hash, Alistair Francis, 2024/01/10
- [PULL 42/65] target/riscv/tcg: add hash table insert helpers, Alistair Francis, 2024/01/10
- [PULL 44/65] target/riscv/tcg: validate profiles during finalize, Alistair Francis, 2024/01/10
- [PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion, Alistair Francis, 2024/01/10
- [PULL 46/65] target/riscv: add 'rva22u64' CPU, Alistair Francis, 2024/01/10
- [PULL 47/65] target/riscv: implement svade, Alistair Francis, 2024/01/10
- [PULL 48/65] target/riscv: add priv ver restriction to profiles, Alistair Francis, 2024/01/10
- [PULL 49/65] target/riscv/cpu.c: finalize satp_mode earlier, Alistair Francis, 2024/01/10
- [PULL 50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit(), Alistair Francis, 2024/01/10
- [PULL 51/65] target/riscv: add satp_mode profile support, Alistair Francis, 2024/01/10
- [PULL 52/65] target/riscv: add 'parent' in profile description,
Alistair Francis <=
- [PULL 53/65] target/riscv: add RVA22S64 profile, Alistair Francis, 2024/01/10
- [PULL 54/65] target/riscv: add rva22s64 cpu, Alistair Francis, 2024/01/10
- [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket, Alistair Francis, 2024/01/10
- [PULL 56/65] linux-headers: Update to Linux v6.7-rc5, Alistair Francis, 2024/01/10
- [PULL 57/65] linux-headers: riscv: add ptrace.h, Alistair Francis, 2024/01/10
- [PULL 63/65] target/riscv: Assert that the CSR numbers will be correct, Alistair Francis, 2024/01/10
- [PULL 61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4, Alistair Francis, 2024/01/10
- [PULL 62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0, Alistair Francis, 2024/01/10
- [PULL 58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize(), Alistair Francis, 2024/01/10
- [PULL 59/65] target/riscv/kvm: add RVV and Vector CSR regs, Alistair Francis, 2024/01/10