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qemu-riscv (date)
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Last Modified: Wed Oct 31 2018 18:49:39 -0400
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October 31, 2018
Re: [Qemu-riscv] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators
,
Richard Henderson
,
18:49
Re: [Qemu-riscv] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
,
Richard Henderson
,
18:47
Re: [Qemu-riscv] [PATCH v3 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
,
Richard Henderson
,
18:45
Re: [Qemu-riscv] [PATCH v3 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
,
Richard Henderson
,
18:44
Re: [Qemu-riscv] [PATCH v3 31/35] target/riscv: Convert @cs_2 insns to share translation functions
,
Richard Henderson
,
18:42
Re: [Qemu-riscv] [PATCH v3 27/35] target/riscv: Remove manual decoding of RV32/64M insn
,
Richard Henderson
,
18:40
Re: [Qemu-riscv] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Richard Henderson
,
18:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Richard Henderson
,
18:28
Re: [Qemu-riscv] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Richard Henderson
,
18:26
Re: [Qemu-riscv] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Richard Henderson
,
18:26
Re: [Qemu-riscv] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Richard Henderson
,
18:22
Re: [Qemu-riscv] [PATCH v3 23/35] target/riscv: Remove manual decoding from gen_store()
,
Richard Henderson
,
18:09
Re: [Qemu-riscv] [PATCH v3 22/35] target/riscv: Remove manual decoding from gen_load()
,
Richard Henderson
,
18:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 20/35] target/riscv: Remove gen_jalr()
,
Alistair
,
16:50
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 11/35] target/riscv: Convert RV64A insns to decodetree
,
Alistair
,
16:49
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 08/35] target/riscv: Convert RVXI csr insns to decodetree
,
Alistair
,
16:46
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Alistair Francis
,
16:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 09/35] target/riscv: Convert RVXM insns to decodetree
,
Alistair
,
16:38
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 07/35] target/riscv: Convert RVXI fence insns to decodetree
,
Alistair
,
16:30
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Alistair
,
16:29
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 05/35] target/riscv: Convert RV64I load/store insns to decodetree
,
Alistair
,
16:26
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC
,
Alistair
,
16:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
,
Alistair Francis
,
16:14
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 0/5] Connect a PCIe host and graphics support to RISC-V
,
Alistair Francis
,
16:11
Re: [Qemu-riscv] [PATCH v3 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Richard Henderson
,
13:15
Re: [Qemu-riscv] [PATCH v3 05/35] target/riscv: Convert RV64I load/store insns to decodetree
,
Richard Henderson
,
13:14
Re: [Qemu-riscv] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
,
Richard Henderson
,
13:12
Re: [Qemu-riscv] [PATCH v3 03/35] target/riscv: Convert RVXI branch insns to decodetree
,
Richard Henderson
,
13:12
Re: [Qemu-riscv] [Qemu-devel] [PULL 2/3] Add Alistair as a RISC-V Maintainer
,
Palmer Dabbelt
,
11:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 0/5] Connect a PCIe host and graphics support to RISC-V
,
Andrea Bolognani
,
10:51
[Qemu-riscv] [PATCH v3 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 22/35] target/riscv: Remove manual decoding from gen_load()
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 31/35] target/riscv: Convert @cs_2 insns to share translation functions
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 20/35] target/riscv: Remove gen_jalr()
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 15/35] target/riscv: Convert RV64D insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 28/35] target/riscv: Rename trans_arith to gen_arith
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 16/35] target/riscv: Convert RV priv insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 05/35] target/riscv: Convert RV64I load/store insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 00/35] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 07/35] target/riscv: Convert RVXI fence insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 11/35] target/riscv: Convert RV64A insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 23/35] target/riscv: Remove manual decoding from gen_store()
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch()
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 08/35] target/riscv: Convert RVXI csr insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 12/35] target/riscv: Convert RV32F insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 04/35] target/riscv: Convert RV32I load/store insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 09/35] target/riscv: Convert RVXM insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 14/35] target/riscv: Convert RV32D insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 30/35] target/riscv: Remove decode_RV32_64G()
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 27/35] target/riscv: Remove manual decoding of RV32/64M insn
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 29/35] target/riscv: Remove gen_system()
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 13/35] target/riscv: Convert RV64F insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 10/35] target/riscv: Convert RV32A insns to decodetree
,
Bastian Koppelmann
,
09:54
[Qemu-riscv] [PATCH v3 03/35] target/riscv: Convert RVXI branch insns to decodetree
,
Bastian Koppelmann
,
09:54
October 30, 2018
[Qemu-riscv] [PATCH v6 4/5] hw/riscv/sifive_u: Connect the Xilinx PCIe
,
Alistair Francis
,
18:22
[Qemu-riscv] [PATCH v6 5/5] hw/riscv/virt: Connect a VirtIO net PCIe device
,
Alistair Francis
,
18:22
[Qemu-riscv] [PATCH v6 3/5] riscv: Enable VGA and PCIE_VGA
,
Alistair Francis
,
18:22
[Qemu-riscv] [PATCH v6 2/5] hw/riscv/virt: Connect the gpex PCIe
,
Alistair Francis
,
18:22
[Qemu-riscv] [PATCH v6 1/5] hw/riscv/virt: Increase the number of interrupts
,
Alistair Francis
,
18:22
[Qemu-riscv] [PATCH v6 0/5] Connect a PCIe host and graphics support to RISC-V
,
Alistair Francis
,
18:22
Re: [Qemu-riscv] [Qemu-devel] [PULL 2/3] Add Alistair as a RISC-V Maintainer
,
Alistair Francis
,
17:33
[Qemu-riscv] [PULL 3/3] Add address@hidden as the RISC-V list
,
Palmer Dabbelt
,
17:23
[Qemu-riscv] [PULL 2/3] Add Alistair as a RISC-V Maintainer
,
Palmer Dabbelt
,
17:23
[Qemu-riscv] [PR RFC] RISC-V Patches for the 3.1 Soft Freeze, Part 2
,
Palmer Dabbelt
,
17:23
[Qemu-riscv] [PULL 1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
,
Palmer Dabbelt
,
17:23
Re: [Qemu-riscv] [Qemu-devel] [PATCH] Add address@hidden as the RISC-V list
,
Philippe Mathieu-Daudé
,
16:01
Re: [Qemu-riscv] [Qemu-devel] [PATCH] Add address@hidden as the RISC-V list
,
Alistair Francis
,
16:01
Re: [Qemu-riscv] [Qemu-devel] [PATCH] Add address@hidden as the RISC-V list
,
Alistair Francis
,
16:01
[Qemu-riscv] [PATCH] Add address@hidden as the RISC-V list
,
Palmer Dabbelt
,
13:48
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