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Re: how to use $^ automatic variable with prerequisites built on target-
Re: how to use $^ automatic variable with prerequisites built on target-specific variable ?
Sat, 10 Jul 2010 08:12:14 +0200
* Axel wrote on Fri, Jul 09, 2010 at 11:32:45AM CEST:
> >I m using a target with prerequisites based on target-specific variable,
> >but it seems that the $^ doesn't work and is empty in this use-case :
> > touch prereq
> >test: FILE = prereq
> >test: $(FILE)
> > echo Variable: $(FILE) Prereq: $^
> >"make test" displays that $^ is empty, but the prerequesites are checked
> >and built. Is this a normal behaviour ? The workaround for me is to use
> >$(FILE) rather than $^ but I assumed that $^ would have worked.
> I ll add that the prerequisites are not built when using this
> syntax, the prereq target is never processed.
This question is mainly about a GNU make feature (target-specific
variables) rather than about Automake (which doesn't understand this
feature). So further questions are better asked on a mailing list about
GNU make such as help-make at gnu.org. Note that Automake provides a
feature of a similar name but different semantics in that it allows for
per-target flags such as, when prog is a program to be built, you can
in order to override
I guess I should also note that Automake encourages using portable make.
Now to your actual question about target-specific variables: I think the
issue is that make expands makefiles in basically two stages: the list
of prerequisites is expanded before it is decided which targets to
remake. I don't think the target-specific variables are expanded for
the prerequisite list expansion already, only for the rule commands of
some target (which you had to find out is too late for you). I think
that `info make Target-specific' does not explain this very well, so you
might want to ask the GNU make maintainer about improving the manual a