${OBJEXT} in implicit rule

[Jan Engelhardt]

Using automake-1.13.4, when using the following Makefile.am fragment,

---8<---
bin_PROGRAMS = foo
foo_SOURCES = foo.c bar.k
.k.${OBJEXT}:
        gcc -x c -c $< -o $@
--->8---

I observe that bar.o is not built and not linked into foo.

---8<---
> make V=0
  CC       foo.o
  CCLD     foo
/usr/lib64/gcc/x86_64-suse-linux/4.8/../../../../lib64/crt1.o: In function
 `_start':
/home/abuild/rpmbuild/BUILD/glibc-2.19/csu/../sysdeps/x86_64/start.S:118:
/undefined reference to `main'
collect2: error: ld returned 1 exit status
Makefile:338: recipe for target 'foo' failed
make: *** [foo] Error 1
--->8---

Interestingly, using $(OBJEXT) instead of ${OBJEXT} gives a successful
build, so I suspect that automake's parser is lacking in some spot.