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Re: [avr-chat] What happens to Timer 1 PWM in sleep?

From: Joerg Wunsch
Subject: Re: [avr-chat] What happens to Timer 1 PWM in sleep?
Date: Tue, 8 Feb 2011 22:33:06 +0100 (MET)

Rick Mann <address@hidden> wrote:

> Power-down is the most power-conservative state, and only pin
> change, TWI address match, and the WDT can wake it up.

External (non-pinchange) interrupts can also wake it up.

> Power-save is the next lowest power mode, and allows a real-time
> clock to keep running.

Right, assuming you've got an asynchronously clocked (usually by a
32768 Hz crystal) timer 2.

> Standby is next, but doesn't allow an RTC.

Standby is mainly there if you've got a crystal or ceramics resonator
as your main clock, yet you need a fast startup time.  Due to their
physics, crystals are notoriously slow in starting up, and reaching a
sufficient oscillator amplitude.

If your device is clocked by the internal RC oscillator, standby (or
extended standby) don't gain you anything.

> Idle
> The last two sleep modes can be used during EEPROM writes, ADC =
> operations, and timer operation.

Nope, ADC noise reduction mode turns off IO clock, so you cannot use
timers.  It's meant to turn off everything that is not needed for the
ADC itself.  (The "Timer Osc enabled" there only refers to the async
mode of timer 2.)

Idle keeps all clocks running, just halting CPU and flash.
cheers, J"org               .-.-.   --... ...--   -.. .  DL8DTL

http://www.sax.de/~joerg/                        NIC: JW11-RIPE
Never trust an operating system you don't have sources for. ;-)

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