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Re: [avr-chat] Problems with xmega DMA Controller

From: Erik Christiansen
Subject: Re: [avr-chat] Problems with xmega DMA Controller
Date: Mon, 11 Apr 2011 19:07:20 +1000
User-agent: Mutt/1.5.17+20080114 (2008-01-14)

On Sat, Apr 09, 2011 at 03:02:31PM -0400, Graham Davies wrote:
> I got this going after another few hours work.  I set up a Counter / 
> Timer to overflow at 1 MHz, routed the Overflow condition over the Event 
> System and used this to trigger the DAC.
> I conclude that the DMA Controller, when configured to trigger from a 
> DAC, is not watching the Data Buffer Empty condition, as I supposed, but 
> is instead somehow tied to whatever is triggering the DAC.  It's not 
> clear to me how this is timed so that the DAC can perform the update, but 
> it appears to work.  Maybe the event causes the contents of the Data 
> Buffer register to load into the conversion hardware and following that 
> the DMA updates the Data Buffer register for the next update.  Anyway, it 
> works.  Phew!


Many thanks for sharing the difficult experience. It's educational for
the rest of us who are only thinking about playing with xmega.

Taking a quick look at the xmega documentation, I'm not sure how you'd
go about trying to make "the Data Register Empty bit" a triggering
event. I was only able to find directions for selecting base and offset
TRIGSRC values for DACB (0x25) + 0x00 for channel 0. (But I didn't spend
much time looking, I'll admit.)

AFAICT, that makes "something" in DACB Channel 0 the trigger for the
DMA channel. It's encouraging that that seems to work, even if the "How"
of it isn't explicit.

Methodical exploration of the DMA novelties, using alternative trigger
sources, was bound to help ecpectation and reality meet, in time. Just
think, if you'd done comp. science instead, you'd have missed out
entirely on these little embedded systems challenges. :-)


"The difference between theory and practice is much smaller in theory
than in practice..."

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