Re: [Bug gas/13215] New: ARM Cortex M3 strexh strexb instructions with same registers generates error

[DaniBoy]

To solve this problem with ARM cortex m3 I changed the supplied CMSIS file
core_cm3.c

I'm now using:
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
   //uint32_t result=0;
   register uint32_t result asm ("r2");
   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r"
(value) );
   return(result);
}
...
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
   //uint32_t result=0;
   register uint32_t result asm ("r2");
   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r"
(value) );
   return(result);
}
instead of:
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
   uint32_t result=0;
   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r"
(value) );
   return(result);
}
...
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
   uint32_t result=0;
   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r"
(value) );
   return(result);
}



Bugzilla from address@hidden wrote:
> 
> http://sourceware.org/bugzilla/show_bug.cgi?id=13215
> 
>              Bug #: 13215
>            Summary: ARM Cortex M3 strexh strexb instructions with same
>                     registers generates error
>            Product: binutils
>            Version: 2.21
>             Status: NEW
>           Severity: critical
>           Priority: P2
>          Component: gas
>         AssignedTo: address@hidden
>         ReportedBy: address@hidden
>     Classification: Unclassified
> 
> 
> Created attachment 5939
>   --> http://sourceware.org/bugzilla/attachment.cgi?id=5939
> example of ARM provided code that makes use of strexh strexb with same
> registers
> 
> In gas version 2.21.53, when compiling for the Cortex-M3 with
> -mcpu=cortex-m3
> -march=armv7-m, the following instructions generate assembler errors:
> 
> strexh r0, r0, [r1]
> strexb r0, r0, [r1]
> 
> The error messages are:
> Error: registers may not be the same -- `strexh r0,r0,[r1]'
> Error: registers may not be the same -- `strexb r0,r0,[r1]'
> 
> However, according to the ARM documentation of STREX for the Cortex M3
> [0],
> only the word sized (32-bit) version of the instruction strex has the
> restriction that the three registers be unique:
> 
> for STREX, Rd must be different from both Rt and Rn
> 
> This problem shows up, for example, when trying to compile vendor provided
> peripheral libraries that make use of CMSIS.  In particular, the
> core_cm3.[ch]
> of CMSIS v1.3, and core_cmInstr.h of CMSIS v2.0 have all of these
> instructions.
>  Curiously, even strex r0, r0, [r1] shows up in CMSIS, even though this is
> explicitly restricted in [0].  So perhaps even some of the CMSIS code is
> breaking the specification of the ARM documentation, not sure.
> 
> [0] --
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABFFBJB.html
> 
> -- 
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