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[Bug ld/21458] ld generates none ARM elf ABI compliant code that causes

From: nickc at redhat dot com
Subject: [Bug ld/21458] ld generates none ARM elf ABI compliant code that causes a hard fault.
Date: Wed, 10 May 2017 12:10:34 +0000


--- Comment #7 from Nick Clifton <nickc at redhat dot com> ---
(In reply to Andrew Goedhart from comment #6)

Hi Andrew,

> Unfortunately we may potentially have another problem. When trying to
> generate a test case I came across the following.

>     ADR R0,__testFnPtr
>     BLX R0

> The problem is that the thumb bit is not set ( subw    r0, pc, #8
> results in an even address) and that this code causes a hard fault.
> Now I don't know my assembly as well as I should so there might be
> wrong/missing directives in the above file. Comment welcome

Hmm, it appears that the ADR pseudo-instruction may not actually support
encoding thumb function addresses in the bottom bit.  It is not mentioned
in the description of the instruction in the ARM ARM.  (I am looking at
section A8.8.12 of the ARM DDI 0406C.b document).  

The intent, I think, is that the value loaded by an ADR instruction will
be used by a B or BL instruction, but not a BLX instruction.

Except that there is a special case when the destination register of the 
ADR instruction is the PC and the processor supports the ARMv7 ISA.  
In this cae the instruction acts like a BX instruction.  Prior to ARMv7
however ADR PC, <label> would act as a B instruction.

Changing the behaviour of the ADR instruction now, would I think, be a 
very dangerous thing to do.  Presumably there is already (lots of) code
out there that is using it in its current state, and fixing this bug, if
it really is a bug, would have the potential to break things.

I will however ping the guys at ARM to see if they have an opinion.


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