[Bug gas/22529] AArch64 treats vector register sizes of 8b and 4b as the same thing.

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=22529

--- Comment #1 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot 
gnu.org> ---
The master branch has been updated by Tamar Christina
<address@hidden>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=a3b3345ae62503982698171bcfce0afe23bd8a31

commit a3b3345ae62503982698171bcfce0afe23bd8a31
Author: Tamar Christina <address@hidden>
Date:   Tue Dec 19 12:04:13 2017 +0000

    Add support for V_4B so we can properly reject it.

    Previously parse_vector_type_for_operand was changed to allow the use of 4b
    register size for indexed lane instructions. However this had the
unintended
    side effect of also allowing 4b for normal vector registers.

    Because this support was only partial the rest of the tool silently treated
    4b as 8b and continued. This patch adds full support for 4b so it can be
    properly distinguished from 8b and the correct errors are generated.

    With this patch you still can't encode any instruction which actually
requires
    v<num>.4b but such instructions don't exist so to prevent needing a
workaround
    in get_vreg_qualifier_from_value this was just omitted.

    gas/

        PR gas/22529
        * config/tc-aarch64.c (vectype_to_qualifier): Support
AARCH64_OPND_QLF_V_4B.
        * gas/testsuite/gas/aarch64/pr22529.s: New.
        * gas/testsuite/gas/aarch64/pr22529.d: New.
        * gas/testsuite/gas/aarch64/pr22529.l: New.

    include/

        PR gas/22529
        * opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B.

    opcodes/

        PR gas/22529
        * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.

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