[Bug gas/22871] Encode instructions of 64-bit operand without the REX_W bit

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=22871

--- Comment #23 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot 
gnu.org> ---
The master branch has been updated by H.J. Lu <address@hidden>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b6f8c7c45229a8a5405079e586bfbaad396d2cbe

commit b6f8c7c45229a8a5405079e586bfbaad396d2cbe
Author: H.J. Lu <address@hidden>
Date:   Tue Feb 27 07:36:33 2018 -0800

    x86: Add -O[2|s] assembler command-line options

    On x86, some instructions have alternate shorter encodings:

    1. When the upper 32 bits of destination registers of

    andq $imm31, %r64
    testq $imm31, %r64
    xorq %r64, %r64
    subq %r64, %r64

    known to be zero, we can encode them without the REX_W bit:

    andl $imm31, %r32
    testl $imm31, %r32
    xorl %r32, %r32
    subl %r32, %r32

    This optimization is enabled with -O, -O2 and -Os.
    2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
    immediate to 64-bit destination register, we can use it to encode 64-bit
    mov with 32-bit immediates.  This optimization is enabled with -O, -O2
    and -Os.
    3. Since the upper bits of destination registers of VEX128 and EVEX128
    instructions are extended to zero, if all bits of destination registers
    of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
    encoding to encode AVX256 or AVX512 instructions.  When 2 source
    registers are identical, AVX256 and AVX512 andn and xor instructions:

    VOP %reg, %reg, %dest_reg

    can be encoded with

    VOP128 %reg, %reg, %dest_reg

    This optimization is enabled with -O2 and -Os.
    4. 16-bit, 32-bit and 64-bit register tests with immediate may be
    encoded as 8-bit register test with immediate.  This optimization is
    enabled with -Os.

    This patch does:

    1. Add {nooptimize} pseudo prefix to disable instruction size
    optimization.
    2. Add optimize to i386_opcode_modifier to tell assembler that encoding
    of an instruction may be optimized.

    gas/

        PR gas/22871
        * NEWS: Mention -O[2|s].
        * config/tc-i386.c (_i386_insn): Add no_optimize.
        (optimize): New.
        (optimize_for_space): Likewise.
        (fits_in_imm7): New function.
        (fits_in_imm31): Likewise.
        (optimize_encoding): Likewise.
        (md_assemble): Call optimize_encoding to optimize encoding.
        (parse_insn): Handle {nooptimize}.
        (md_shortopts): Append "O::".
        (md_parse_option): Handle -On.
        * doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
        as {nooptimize}.
        * testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
        * testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
        * testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
        optimize-3, x86-64-optimize-1, x86-64-optimize-2,
        x86-64-optimize-3 and x86-64-optimize-4.
        * testsuite/gas/i386/optimize-1.d: New file.
        * testsuite/gas/i386/optimize-1.s: Likewise.
        * testsuite/gas/i386/optimize-2.d: Likewise.
        * testsuite/gas/i386/optimize-2.s: Likewise.
        * testsuite/gas/i386/optimize-3.d: Likewise.
        * testsuite/gas/i386/optimize-3.s: Likewise.
        * testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
        * testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
        * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
        * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
        * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
        * testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
        * testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
        * testsuite/gas/i386/x86-64-optimize-4.s: Likewise.

    opcodes/

        PR gas/22871
        * i386-gen.c (opcode_modifiers): Add Optimize.
        * i386-opc.h (Optimize): New enum.
        (i386_opcode_modifier): Add optimize.
        * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
        "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
        "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
        "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
        vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
        vpxord and vpxorq.
        * i386-tbl.h: Regenerated.

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