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From: | cvs-commit at gcc dot gnu.org |
Subject: | [Bug gas/23956] RISC-V 4-operand add doesn't check for %tprel_add |
Date: | Fri, 07 Dec 2018 20:32:19 +0000 |
https://sourceware.org/bugzilla/show_bug.cgi?id=23956 --- Comment #2 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jim Wilson <address@hidden>: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f50fabe4f66534c9addacddeaa439e8d164eadda commit f50fabe4f66534c9addacddeaa439e8d164eadda Author: Jim Wilson <address@hidden> Date: Fri Dec 7 12:31:05 2018 -0800 RISC-V: Fix 4-arg add parsing. PR gas/23956 gas/ * config/tc-riscv.c (validate_riscv_insn) <'1'>: New case. (percent_op_null): New. (riscv_ip) <'j'>: Set imm_reloc before p. <'1'>: New case. <'0'>: Use percent_op_null and don't set imm_reloc. <alu_op>: Handle *args == '1'. * testsuite/gas/riscv/tprel-add.d: New. * testsuite/gas/riscv/tprel-add.l: New. * testsuite/gas/riscv/tprel-add.s: New. opcodes/ * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg. -- You are receiving this mail because: You are on the CC list for the bug.
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