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[Bug ld/24226] Need advise on the binutils problem that generating wrong
From: |
wilson at gcc dot gnu.org |
Subject: |
[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend |
Date: |
Mon, 18 Feb 2019 23:55:30 +0000 |
https://sourceware.org/bugzilla/show_bug.cgi?id=24226
Jim Wilson <wilson at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |wilson at gcc dot gnu.org
--- Comment #1 from Jim Wilson <wilson at gcc dot gnu.org> ---
The medany explicit-relocs problem is different than the one here. This
requires an auipc to trigger, and there is no auipc here.
This looks like a compiler bug if this is compiler generated code, or a
programmer error if this is hand written assembly code. It is not safe to use
lw a3,%lo(g_3030+4)(a5)
unless g_3030 has 8-byte alignment, and if it does, then the %lo can not
overflow.
The current linker sources will give an error if it detects an auipc/lw
overflow, but I hadn't considered this case with an incorrect lui/lw
instruction pair. Even though this is compiler/user error, it would still be
useful if the linker gave an error for it instead of silently producing
incorrect code, as finding this incorrect code after the fact is likely to be
hard.
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- [Bug ld/24226] New: Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend, liuyingying19 at huawei dot com, 2019/02/18
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend,
wilson at gcc dot gnu.org <=
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend, wilson at gcc dot gnu.org, 2019/02/18
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend, liuyingying19 at huawei dot com, 2019/02/18
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend, wilson at gcc dot gnu.org, 2019/02/19
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend, liuyingying19 at huawei dot com, 2019/02/19