[Bug gas/25550] Review .arch directives

[jbeulich at suse dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=25550

--- Comment #9 from Jan Beulich <jbeulich at suse dot com> ---
(In reply to H.J. Lu from comment #8)
> We can say something like
> 
>      In addition to the basic instruction set, the assembler can be told
>      to accept various extension mnemonics.  4 separate vector ISA
>      extension families can be enabled or disabled independent of each
>      other:
> 
>         * 'MMX' - MMX instructions.
> 
>         * 'SSE' - SSE instructions without MMX registers.

This is not a useful category. The only viable options I see are
- the full set of insns valid with SSE* (including ones accessing MMX
registers),
- all insns not touching MMX _state_ (which would permit use of CVTPI2PD with a
memory operand, but not use of a similar CVTPI2PS).

In the latter case special care should be taken to at least warn about Intel
syntax uses like "CVTPI2PD xmm0, mm0", as from simply looking at such an insn
one wouldn't tell it uses a memory operand named "mm0".

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