[Bug gas/27436] RISC-V inconsistent handling of rv32 shift with count > 31

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=27436

--- Comment #2 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot 
gnu.org> ---
The master branch has been updated by Nelson Chu <nelsonc1225@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=768589d18042a55f0e1f77f466568a1c102ab099

commit 768589d18042a55f0e1f77f466568a1c102ab099
Author: Nelson Chu <nelson.chu@sifive.com>
Date:   Fri Apr 16 14:50:32 2021 +0800

    RISC-V: PR27436, make operand C> work the same as >.

    gas/
        PR 27436
        * config/tc-riscv.c (riscv_ip): make operand C> work the same as >.
        * testsuite/gas/riscv/shamt-32.d: New testcase.
        * testsuite/gas/riscv/shamt-32.l: Likewise.
        * testsuite/gas/riscv/shamt-32.s: Likewise.
        * testsuite/gas/riscv/shamt-64.d: Likewise.
        * testsuite/gas/riscv/shamt-64.l: Likewise.
        * testsuite/gas/riscv/shamt-64.s: Likewise.

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