[Bug gas/27436] RISC-V inconsistent handling of rv32 shift with count > 31

[nelsonc1225 at sourceware dot org]

https://sourceware.org/bugzilla/show_bug.cgi?id=27436

Nelson Chu <nelsonc1225 at sourceware dot org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
                 CC|                            |nelsonc1225 at sourceware dot 
org
             Status|NEW                         |RESOLVED

--- Comment #3 from Nelson Chu <nelsonc1225 at sourceware dot org> ---
Now I can have the expected results by using mainline binutils,

nelson@LAPTOP-QFSGI1F2:~$ riscv32-unknown-elf-as -march=rv64g tmp.s
nelson@LAPTOP-QFSGI1F2:~$ riscv32-unknown-elf-as -march=rv64gc tmp.s
nelson@LAPTOP-QFSGI1F2:~$ riscv32-unknown-elf-as -march=rv32g tmp.s
tmp.s: Assembler messages:
tmp.s:1: Error: improper shift amount (63)
nelson@LAPTOP-QFSGI1F2:~$ riscv32-unknown-elf-as -march=rv32gc tmp.s
tmp.s: Assembler messages:
tmp.s:1: Error: improper shift amount (63)

I convert the immediate to unsigned long first, and then only check if it is
invalid when the value >= xlen.  This is the same as the checking of operand
'>'.

Marked as Resolved and Fixed.  If the above behavior has risk, then we can
reopen the PR and use another way to fix it.

Thanks

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