[Bug binutils/29342] New: RISC-V 32: disassembly mishandles symbols

[hpa at zytor dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=29342

            Bug ID: 29342
           Summary: RISC-V 32: disassembly mishandles symbols
           Product: binutils
           Version: 2.38
            Status: UNCONFIRMED
          Severity: normal
          Priority: P2
         Component: binutils
          Assignee: unassigned at sourceware dot org
          Reporter: hpa at zytor dot com
  Target Milestone: ---

It is common on embedded systems to put I/O registers in the high half of the
address space; on RISC-V it is particularly desirable to put address space for
I/O devices which only need a limited number of addresses in the high 2K, which
means they can be addressed using negative offsets from (zero), avoiding the
need for a base pointer.

However, objdump disassembly shows addresses in the upper half of the address
space as offsets from the highest-addressed symbol (possibly due to incorrectly
treating them as 64-bit numbers before searching?)

The result means disassembly is needlessly hard to read:

        iobase = 0xffffff00

        .globl IOREG_FOO
IOREG_FOO       = iobase
        .globl IOREG_BAR
IOREG_BAR       = iobase + 4

        .section ".text","ax"
        .globl _start
_start:
        .if iobase >= 0xfffff800
        sw a0, IOREG_FOO(zero)
        .else
        la t0, IOREG_FOO
        sw a0, (t0)
        .endif
        ret

riscv32-unknown-elf-as -march=rv32i -o highsym.o highsym.s
riscv32-unknown-elf-ld -o highsym.elf highsym.o
riscv32-unknown-elf-objdump -d highsym.elf
highsym.elf:     file format elf32-littleriscv


Disassembly of section .text:

00010074 <_start>:
   10074:       f0a02023                sw      a0,-256(zero) # ffffff00
<IOREG_BAR+0xfffffffc>
   10078:       00008067                ret

-- 
You are receiving this mail because:
You are on the CC list for the bug.