[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

[olof.kindgren at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=25202

--- Comment #13 from Olof Kindgren <olof.kindgren at gmail dot com> ---
Great to see some activity on this! I haven't compiled and tested it myself
yet, but I'm wondering if we got the addressing right. Nick, it's correct that
we are dealing with word addresses, but are we taking that into consideration
when we're calculating the base address?

I.e. compiling an asm program that starts with .org 0x100, will that cause the
address to be set to @40 when using verilog-data-width=4 ?

Generally, I think you shouldn't trust VerilogDataWith part of the verilog
output too much even if it has been there for a long time. I believe that
practically no one has actually used this feature much because of this bug (and
https://sourceware.org/bugzilla/show_bug.cgi?id=19921 before that) so it's
likely not very well tested.

Liwei Ma, we can already change the base address like you asked for with
--change-addresses (you can find an example here
https://github.com/chipsalliance/Cores-SweRVolf/blob/master/sw/Makefile#L27)

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