[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

[sourceware.org at aydos dot de]

https://sourceware.org/bugzilla/show_bug.cgi?id=25202

--- Comment #22 from Gökçe Aydos <sourceware.org at aydos dot de> ---
I browsed LRM section 21.4 about `$readmemh`, but could not find any info about
maximum width (for a memory line that is read by `$readmemh`). I think the
range is limited by the maximum width of a vector (`logic`, `bit` etc). Section
6.9.1 states:

> Implementations may set a limit on the maximum length of a vector,
> but the limit shall be at least 65536 (2^16) bits.

I tried to read 1024 bits with Verilator and Vivado. Both tries succeeded.
Practically I know that 1024 bit memories exist, e.g.,
[HBM](https://en.wikipedia.org/wiki/High_Bandwidth_Memory#HBM3). Nevertheless I
concur what Olof said: people will typically use 32 to 128 bits and when people
will start using objdump, then someone will fix the max 16 byte width.

FWIW here are the files I used for testing:

a.sv:
```
module a;

logic[1023:0] mem [int];
logic clk = 0;

initial begin
    $readmemh("a.memh", mem);
    foreach (mem[i])
        $display("mem[%0d] = %0d", i, mem[i]);
    $finish;
end

always #1 clk ^= 1;

endmodule
```

a.memh
```
01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde01234567890abcde
```

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