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[Bug gas/29940] New: fails to correctly assemble the JAL instruction on


From: aurelien at aurel32 dot net
Subject: [Bug gas/29940] New: fails to correctly assemble the JAL instruction on riscv64
Date: Sun, 25 Dec 2022 14:57:52 +0000

https://sourceware.org/bugzilla/show_bug.cgi?id=29940

            Bug ID: 29940
           Summary: fails to correctly assemble the JAL instruction on
                    riscv64
           Product: binutils
           Version: unspecified
               URL: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1026
                    979
            Status: NEW
          Severity: critical
          Priority: P2
         Component: gas
          Assignee: unassigned at sourceware dot org
          Reporter: aurelien at aurel32 dot net
                CC: jbeulich at suse dot com
  Target Milestone: ---
              Host: riscv64-unknown-linux-gnu
            Target: riscv64-unknown-linux-gnu
             Build: riscv64-unknown-linux-gnu

inutils on riscv64 fails to correctly assemble the JAL instruction when
used without implicit register, that is in the format JAL reg, imm.
This can be reproduced with this simple test program:

.text
1:
    jal zero, 1b

With recent binutils versions, "zero" is not interpreted as a register,
but instead as the immediate value, and therefore a relocation is
emitted. This happens also when using other register names such as "a1"
or "x0". This causes the linux packages to fails to build due to
unresolved symbols in kernel modules:

ERROR: modpost: "zero" [arch/riscv/kvm/kvm.ko] undefined!
ERROR: modpost: "zero" [mm/z3fold.ko] undefined!
ERROR: modpost: "zero" [fs/mbcache.ko] undefined!
ERROR: modpost: "zero" [fs/fscache/fscache.ko] undefined!
ERROR: modpost: "zero" [fs/jbd2/jbd2.ko] undefined!
ERROR: modpost: "zero" [fs/nfs/nfs.ko] undefined!
ERROR: modpost: "zero" [fs/nfs/nfsv4.ko] undefined!
ERROR: modpost: "zero" [fs/nfsd/nfsd.ko] undefined!
ERROR: modpost: "zero" [fs/ufs/ufs.ko] undefined!
ERROR: modpost: "zero" [fs/xfs/xfs.ko] undefined!

The issue has been introduced by this commit:

commit 839189bc932ea02c9647a3ad829dda72f8a9562c
Author: Jan Beulich <jbeulich@suse.com>
Date:   Fri Sep 30 10:19:00 2022 +0200

    RISC-V: re-arrange opcode table for consistent alias handling

    For disassembly to pick up aliases in favor of underlying insns (helping
    readability in the common case), the aliases need to come ahead of the
    "base" insns. Slightly more code movement is needed because of insns
    with the same name needing to stay next to each other.

    Note that the "rorw" alias entry also has the missing INSN_ALIAS added
    here.

    Clone a few testcases to exercise -Mno-aliases some more, better
    covering the differences between the default and that disassembly mode.

Reverting the first hunk of the opcodes/riscv-opc.c patch fixes the issue.

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