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Vectorized assembler routines for IA-64
From: |
Bob Deblier |
Subject: |
Vectorized assembler routines for IA-64 |
Date: |
Wed, 2 May 2001 13:08:34 +0200 |
Dear,
I'm experimenting with vectorized multi-precision assembler routines for the
IA-64 processor.
I currently have working optimized routines equivalent to add_n and addmul_1,
tested on Suse's compile farm. If you're interested, it will be very easy for
me to convert to my routines to a version suitable for GMP. The addmul
routine will require only a re-ordering of the parameters, while the addition
routine would require some minor work.
Please let me know if you're interested in this contribution.
Sincerely,
Bob Deblier
Virtual Unlimited
- Vectorized assembler routines for IA-64,
Bob Deblier <=