bad vhdl code for busses (busvhdl)

[Tuukka Toivonen]

This is something that right now stops me from simulating my
schematics. A quick fix/workaround would be very much appreciated,
otherwise I'll go and look if I can modify VHDL compiler to just ignore
errors of this type.

BUG: VHDL generator generates incorrect code if different width busses
     are connected (by name) in a schematics
SYM: load bug-busvhdl.txt and select Tools/Simulation/Simulate.
     Electric says:
---
Converting layout in facet test{sch}, writing VHDL to facet test{vhdl}
ERROR on line 9, Signal previously defined:
signal s_0_, s_1_, s_2_, s_3_, s_2_, s_3_, s_0_, s_1_: BIT; 
                               ^
---
Because the generated VHDL looks like
---
entity test is port(i1, i2, i3, i4: in BIT; e1, e2: out BIT);
  end test;
architecture test_BODY of test is
  component buffer port(a: in BIT; y: out BIT);
    end component;
  component and2 port(a1, a2: in BIT; y: out BIT);
    end component;
  signal s_0_, s_1_, s_2_, s_3_, s_2_, s_3_, s_0_, s_1_: BIT;
begin
  node12: buffer port map(i4, s_3_);
  node11: buffer port map(i3, s_2_);
  node10: and2 port map(s_2_, s_3_, e2);
  node6: buffer port map(i2, s_1_);
  node5: buffer port map(i1, s_0_);
  node2: and2 port map(s_0_, s_1_, e1);
end test_BODY;
---
VER: 6.04

bug-busvhdl.txt
Description: Text document