CG-CoreEl is pleased to invite you for a free technical seminar which
will address today's complex verification challenges and
requirements for system and mixed-signal designs.
Functional verification is a critical bottleneck in the delivery of today's highly complex electronics systems. Keeping pace with ever shrinking market windows and increasing design complexities dictates the adoption of advanced verification methodologies.
This one-day seminar will provide an overview of Mentor Graphics' comprehensive solutions for each level of the verification process, encompassing block, sub-system, system and full chip verification. Invited specialists will explore the use of a single-kernel verification environment in
verifying complex analog/mixed-signal/RF designs. This verification environment supports both top-down and bottom-up methodologies as well as behavioral
modeling such as VHDL-AMS, Verilog-AMS and C models. The importance of verifying the embedded software in a hardware/software co-verification environment will also be demonstrated, as the amount of embedded software is increasing in today's complex design to ensure first-pass
success.
Keynote Speaker Brian Bailey:
Brian Bailey, Chief Technologist, Mentor Graphics Design Verification and Test Division, has over 20 years of verification tool expertise, including development of the first RTL simulator, emulators, accelerators, and hardware/software co-simulation plus years of consulting with large companies on their verification issues. Brian has several patents, and has presented at numerous conferences over the years and currently chairs the Accellera technical committee for interfaces. Brian has also contributed to a book on SoC methodologies. |
Attend this free technical seminar to gain valuable insights on overcoming today's challenges of verification of complex digital designs.
Seminar seats fill up quickly, so submit your registration request today!
Details and online registration at
http://www.cg-coreel.com/register/verification
Who should attend:
- Hardware Designers
- Embedded Software Developers
- Verification Engineers
- Project Managers
| Seminar
Agenda |
| 9:00 AM |
Registration and refreshments |
| 9:30
AM |
Keynote Address: Verification Overview- Brian Bailey, Chief Technologist, Mentor Graphics Corporation |
| 10:30 AM |
Analog Mixed-Signal Simulation: ADvance MS- Jeff Laster, Product Specialist Consultant, Mentor Graphics Corporation |
| 11:15 AM |
All-in-One: ModelSim- Simon Ho, HDL Product Marketing Manager (PacRim), Mentor Graphics Asia |
| 12:00 PM |
Lunch |
| 1:00 PM |
RF Mixed-Signal Simulation: Eldo RF and ADMS RF |
| 2:00 PM |
Accelerated HW/SW Co-Simulation- Thomas Li, Technical Manager (PacRim), Mentor Graphics (Taiwan) |
| 3:00 PM |
Wrap-up |
|
Seminar Schedule: |
| July 21 |
Napoleon 1, Le Meridian,
New Delhi, India |
| July 23 |
Royal Ball Room, Hotel Leela Palace,
Bangalore, India |
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