Electric 6.08 bug?

[jah]

This VHDL causes the silicon compiler to barf (SEGV);

-- VHDL automatically generated from facet XNOR_WITH_MASK{sch}
entity XNOR_WITH_MASK is port(M_H, A_H, B_H: in BIT; Q_H: out BIT);
  end XNOR_WITH_MASK;
architecture XNOR_WITH_MASK_BODY of XNOR_WITH_MASK is
  component or2 port(a1, a2: in BIT; y: out BIT);
    end component;
  component xor2 port(a1, a2: in BIT; y: out BIT);
    end component;
  component inverter port(a: in BIT; y: out BIT);
    end component;
  signal net1: BIT;
  signal PINV1, PINV2: BIT;
begin
  or1: or2 port map(PINV1, PINV2, Q_H);
  xor1: xor2 port map(B_H, A_H, net1);
  PSEUDO_INVERT1: inverter port map(net1, PINV1);
  PSEUDO_INVERT2: inverter port map(M_H, PINV2);
end XNOR_WITH_MASK_BODY;

The "Do Placement" command pops a dialog stating FATAL ERROR: A
segmentation violation has occurred.

Is this a known issue with Electric? Any fix or workaround?

Cheers,

/.J