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Re: Stack base and thread-specific data

From: Roland McGrath
Subject: Re: Stack base and thread-specific data
Date: Wed, 8 Aug 2001 22:50:46 -0400 (EDT)

Even without kernel limitations, you'd use up most of the address space
with thread stacks (even small ones), and not have much left for the
presumably large amount of data you'd be operating on if you needed so many
threads, before you hit those limits.  

There are also other kernel-assisted approaches to simulate a spare
register to dedicate to a per-thread value that are easy implement and
don't have such limitations.  e.g., having %gs:0 fixed at a location the
kernel writes with a per-thread value on context switch.  This approach
might also perform better since if you aren't using an LDT then Mach
doesn't do an x86 "task switch" at all for a context switch (and perhaps
the single store is cheaper).

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