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Re: SMP, barriers, etc.

From: Da Zheng
Subject: Re: SMP, barriers, etc.
Date: Fri, 01 Jan 2010 18:33:30 +0800
User-agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv: Gecko/20091204 Thunderbird/3.0

On 09-12-28 下午8:32, Samuel Thibault wrote:
>> So when a write memory barrier instruction is executed, the processor
>> has to remember the order of writes, so the read memory barrier
>> instruction executed on another processor can somehow get the
>> information?
> In principle, yes. The actual implementation in the hardware cache
> coherency protocol can be a barrier that prevents reordering, or
> sequential numbers, etc.
I think I get some vague ideas about barriers and cache coherency now. I really
should take some courses about multiprocessor architectures when I was at
school. Unfortunately, my school only has this kind of course after I left it:-(

Thank you very much for your explanation, Samuel.

Zheng Da

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