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Re: cache coherency in DMA and MMIO

From: Da Zheng
Subject: Re: cache coherency in DMA and MMIO
Date: Sun, 02 May 2010 20:36:28 +0800
User-agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv: Gecko/20100317 Thunderbird/3.0.4

On 10-4-23 下午7:37, Samuel Thibault wrote:
> Depends on how you use the mem device. It it ends up using pmap_enter()
> to actually fill the page table, it will notice whether your physical
> addresses are within RAM or above, see the code there.
I think I find the code to do that.
            if (machine_slot[cpu_number()].cpu_type >= CPU_TYPE_I486
                && pa >= phys_last_addr)
                template |= INTEL_PTE_NCACHE|INTEL_PTE_WTHRU;
The MMIO address of e1000 is at 0xd8920000 and 0xd8900000. I even insert print
in the code to confirm that the MMIO address has been set non-cache.

Zheng Da

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