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Dependency - but not really

From: Oelke, Dan
Subject: Dependency - but not really
Date: Thu, 22 Feb 2001 18:02:16 -0600

Ok - I'm not sure how to do this, but what I want is a dependency for one
target, BUT I don't want that dependency to be evaluated.  

Some background - I have a makefile that sets up a few variables, and then
includes a "helper".  This allows our developers to not care about how to
write a makefile to build 6 different targets and all the options, etc.
This helper gets included repeatedly - once for each "subsystem" that is
defined.  A subsystem is defined by setting a half dozen or so variables and
then including this helper.

A snippet of the helper is as follows:

# Compile rules for a subsystem


$($(SUBSYSTEM)_C_Objs): obj/%.o: %.c $(SUBSYSTEM)_
        $(CC_T) $(T_CFLAGS) $($(filter-out %.c,$+)CFLAGS) -c $< -o $@

The CC_T line needs to access the SUBSYSTEM variable, but since SUBSYSTEM
gets redefined repeatedly, it isn't there when it comes time to evaluate
that line.  We need the SUBSYSTEM variable to get at the $(SUBSYSTEM_CFLAGS)
value.  So, the quick solution we came up with was to add SUBSYSTEM as a
dependency and then filter it out.  But declaring it as a .PHONY isn't
perfect, as now we need to create a file of the name $(SUBSYSTEM)_ for every
possible SUBSYSTEM value, or the target is always out of date.

SO - does anyone have any good ideas on how to do this without creating the
extra files?



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