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Please Help!- I have a problem using make ( variable "$*")

From: Kang Sujin-W19218
Subject: Please Help!- I have a problem using make ( variable "$*")
Date: Thu, 26 Apr 2001 18:05:49 +0900


I am Sujin,Kang in Seoul, Korea.
I am a Software engineer in Motorola Korea Technology Center.

I did a build using gnu make, perl script and arm compiler.
We have no problem in DOS mode but in UNIX....^^;;;;;;

The problem is concerned with the variable "$*";
For example,

file : 
$(TARGETDIR)/%.o %.o: %.c
        @echo -----------------------------------------------------------------
        @echo OBJECT $@
        @echo $@ $< $* $?
        $(CC) $(CFLAGS) $(DMSS_CFLAGS) $(MSG_FILE) $(OBJ_CMD) $@ $*.c
        @echo $@ $< $*
        @echo ----------------------------------------------------------------
a.min is called from a perl script which is called from a main make file.
The echo results are 
% <= surfcoei/bit_
 echo -----------------------------------------------------------------
 echo OBJECT surfcoei/bit_.o
 echo surfcoei/bit_.o surfcoei/bit_.c bit_ surfcoei/bit_.c
                                                   ^^^^^ this part is the 
I think and I know that variable  "$*" is the base name of target and the 
target minus suffix in implicit rule.
Am I wrong?
If so, I think the echo result has to be not bit_ but surfcoei/bit_. Doesn't it?

What is problem?
I have no idea until now....
please help me and answer it to me.
Thank you for your help and your concern.


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