Re: problems with $(eval include...)

[Peter A. Kerzum]

> Exactly. For the way make is conceived now, once it starts building a
> target it doesn't check for any other rule which have that save target. In
> other words, once make goes to build foo.o, and then it executes a rule
> which imports some other rules for foo.o, those rules are just ignored.
>
> This I think should change, so that my apporach would be seamlessy
> supported.

Yes, this should be nice but I feel there's a sort of algorithmic 
limitation as Paul said. Sorry for a silly question, but is this 
possible to recurse to stage 1 after completing stage 2 if list of 
prerequisites has changed? This should be something similar to recursive 
invocation of make. Though this doesn't look pretty enough may be there 
is quite more granular way. Anyway this is just a thought -- I have no 
clean apprehension of make internals.

> My system is growing up quite nicely, if you're interested I can give you
> you some example code, and explain how does that work. Would be good if we
> could discuss this on an ML, so that other people who are interested may
> join the discussion.

Yes, I'm very interested =) I began with theese requirements:
1. I have modular project with multiple (13) destination binaries. So I 
want to be able to build just one binary [as long as all], without 
touching others and add more binaries easily.
2. I want to be able to change build process for all targets in one 
place (eg add -Dxxx to CFLAGS)
3. I want to support multiarch builds, but in fact I failed to do this

so I came up with this structure:

I have a filesys tree, starting with src/ that contains common sources, 
dirs with modules, short Makefile to build all the modules and one big 
Makefile.def with all the rules and definitions.

src/
        Makefile        [ make all submodules ]
        Makefile.def    [ all the build internals ]
        utils.cc
        module_one/
                module_one.cc
                Makefile        [ build module_one binary ]
        module_two/
                Makefile        [ make all submodules ]
                submodule_one/
                        Makefile        [ build submodule_one binary ]
                        submodule_one.cc
                submodule_two/
                        Makefile        [ build submodule_two binary ]
                        submodule_two.cc

Each Makefile in my case defines target name, list of objects and 
optional additional build action among with additional build options.
Then it searches for Makefile.def and includes it. Real build is driven 
by Makefile.def that builds named target with objects, options and 
actions defined by including Makefile.
So my make is in fact recursive while I moved all the stuff into one 
maintainable place.

This method is definetly not suitable for me =(
Thoulgh I like the control, GNU make gives me over the entire build, for 
a last time I am looking at automake and Jam =)
But I still believe this can be solved with proper use of make

--
Best regards,
Peter A. Kerzum