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Re: Static pattern usage

From: Paul D. Smith
Subject: Re: Static pattern usage
Date: Fri, 3 Oct 2003 17:18:04 -0400

%% Sam Ravnborg <address@hidden> writes:

  sr> deps_foo.o := foo.h

  sr> foo.o : % : $(deps_%) bar.h FORCE
  sr>         @echo $^

  sr> When executed I expected it to print:
  sr> foo.h bar.h FORCE

  sr> But it only prints bar.h FORCE


  sr> Is it coorect behaviour that make does not expand the variable
  sr> $(deps_foo.o)?

Yes, because that's not the variable you asked to expand.  You asked it
to expand the variable $(deps_%).

  sr> % is equal to foo.o in the above example,

No it isn't; or at least it isn't when the prerequisites line is
expanded.  The entire target definition line, including the
prerequisites, is expanded _BEFORE_ the line is parsed.  When expansion
happens the pattern substitution hasn't occurred yet, so you're
expanding a variable named "deps_%" which doesn't exist, and so it
expands to nothing.

See the GNU make manual for a precise description of when expansion
happens in various constructs.

 Paul D. Smith <address@hidden>          Find some GNU make tips at:
 http://www.gnu.org                      http://make.paulandlesley.org
 "Please remain calm...I may be mad, but I am a professional." --Mad Scientist

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