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16 Oct 2003 14:45:30 +0200
GNU Make version 3.79.1, by Richard Stallman and Roland McGrath.
Built for i386-redhat-linux-gnu
and stumbled across a bug/feature which I could not find anywhere in the
documentation, newsgroups or mailing lists (including this one)
concerning the recursive use of wildcards.
The following Makefile
echo $@ requested
is a variation of the popular
$(CC) -c $< -o $@
theme, just with a recursive definition. Calling
works just fine, outputting
echo a1 requested
should, in my opinion, produce the same output. Unfortunately though, I
make: *** No rule to make target `b1'. Stop.
Am I doing something wrong here or is there some magic command or option
I am missing? Or is this a bug/feature?
Cheers and many thanks in advance
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- recursive wildcards,
Pedro Gonnet <=