Re: Using % in a variable name as a static pattern prereq?

[Paul D. Smith]

%% Carl Miller <address@hidden> writes:

  cm> I'm trying to automate building a variety of libraries by using
  cm> static pattern rules and having a variable per library to call out
  cm> what .o files should be included in each library.  The relevant
  cm> portion of the makefile is:

  cm> $(filter %.a,$(TARGETLIBS)) : %.a : $(%_OBJS) 

You can't do this.

As you've discovered, variables and functions are all expanded _BEFORE_
any pattern matching or replacement is performed.

  cm> TARGETLIBS = libfoo.a libfoo.so
  cm> libfoo_OBJS = foo1.o foo2.o foo3.o
  cm> libfoo_SONAMESUFFIX = .0
  cm> libfoo_SOFINALNAME = glibfoo-2.3.2.so

You can do this, but not without using the new $(eval ...) function.

Note that 3.80 has a couple of bugs in the eval area.  There's a beta of
3.81 available (see the archives for these mailing lists) which fixes
them and is, overall, a better bet than 3.80 if you're going to use
these expanded functions.

  cm> And if it's performing "as expected" (this being an
  cm> unexpected/unsupported use of %), could this be taken as a feature
  cm> request to make it work as I'm attempting to use it in the next
  cm> release?

No.  Sometimes people want the variables/functions to be expanded before
pattern matching, sometimes they want them to be expanded after pattern
matching.  The way make works now is the way it has always worked, and I
don't see enough of a reason to make this sort of backward-incompatible
change to its behavior.

Especially since you can do what you want to do with the $(eval ...)
function.

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