make inconsistent

[Sebastian Neuper]

#Hi GNU-make-developers.
#
#I had some problems with this Makefile.
#make printed always the error:
#warning: overriding commands for target xxx
#warning: ignoring old commands for target xxx
#Circular xxx <- yyy dependency dropped.
#
#I asked my teachers and other students, but
#nobody found a mistake. 
#Then I changed the 
#SOURCE = $(PROJ).c to SOURCE = xxx.c
#and it worked. I undo this changed and it
#still worked. Now I have no idea, why.
#I cannot reproduce this 'bug' anymore.
#Can the same Makefile be treated differently?
#
#If this problem occurs again, I will send 
#reproduceable code.
#
#
#Best Regards, Sebastian
#
#GNU Make version 3.79.1, by Richard Stallman and Roland McGrath.
#Built for i386-pc-linux-gnu
#Copyright (C) 1988, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
#        Free Software Foundation, Inc.
#               This is free software; see the source for copying conditions.
#               There is NO warranty; not even for MERCHANTABILITY or FITNESS 
FOR A
#               PARTICULAR PURPOSE.
#
#               Report bugs to <address@hidden>.
#
#!/usr/bin/make
#Makefile

PROJ = xxx
SOURCE = $(PROJ).c
OBJS = $(SOURCE:%.c=%.o)
HEADER = $(PROJ).h
CC = gcc
CFLAGS = -ansi -pedantic -D_XOPEN_SOURCE=500 -Wall -Werror -g

all: $(PROJ)

$(PROJ): $(OBJS)
        @echo make proj of objs: $@ cause of $?
        @echo         \(all prerequisities of $@: $^\)
        $(CC) $(CFLAGS) -o $(PROJ)  $(OBJS)

$(OBJS): $(SOURCE)
        @echo make source to objs: $@ cause of $?
        @echo         \(all prerequisities of $@: $^\)
        $(CC) $(CFLAGS) -c  $(SOURCE)

clean:
        rm -f $(OBJS)
        rm -f $(PROJ)

install: all
        cp $(PROJ) ../bin.i386