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Re: target variable expansion with included make files


From: Boris Kolpackov
Subject: Re: target variable expansion with included make files
Date: Thu, 5 Aug 2004 14:49:06 +0000 (UTC)
User-agent: nn/6.6.5+RFC1522

"Brad Kemp" <address@hidden> writes:

> The main makefile includes two small makefiles.
> Each make file defines variables used in the targets of the other makefile.
> The target names are immediatly expanded which causes the first makefile
> not to use the variables defined in the second makefile in its target names.

That's how make works. Rules are expended as they are read.

> Is there a better approach?

Your example doesn't give any idea what you are trying to achieve so it's
hard to say. Maybe if you describe actual problem we may be able to help.

-boris





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