[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

[Markus Elfring]

URL:
  <http://savannah.gnu.org/bugs/?51292>

                 Summary: Handling make rules where prerequisites are
determined by functions for specific targets lists
                 Project: make
            Submitted by: elfring
            Submitted on: Thu 22 Jun 2017 03:10:13 PM CEST
                Severity: 3 - Normal
              Item Group: Enhancement
                  Status: None
                 Privacy: Public
             Assigned to: None
             Open/Closed: Open
         Discussion Lock: Any
       Component Version: 4.2.1
        Operating System: Any
           Fixed Release: None
           Triage Status: None

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Details:

Static pattern rules
<https://www.gnu.org/software/make/manual/html_node/Static-Usage.html> can be
used like in the following example.


objects::=foo.o bar.o

$(objects): %.o: %.c
        $(CC) -c $(CFLAGS) $< -o $@



Such a specification seems to indicate that the placeholder “%” can only
be mapped to a stem if the passed targets contain the same suffix (and/or
prefix) which was also specified by the target pattern.
I find that this approach requires then the use of duplicate data. I would
prefer to avoid that because of general software design principles
<https://en.wikipedia.org/wiki/Don%27t_repeat_yourself>.

I would prefer in some use cases to work directly with the targets list in the
way by appending (or prepending) something to a file name (instead of
performing the previous data extraction operation).

I imagine that an other syntax variant could express additional possibilities
for a better handling of desired prerequisites there. I suggest to let
customisable callback functions
<https://en.wikipedia.org/wiki/Callback_(computer_programming)> decide which
data transformations should be finally applied.

How do you think about to add support for such advanced generation of make
rules?




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