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[bug #51974] multiline (define/endef) containing target-specific assignm

From: Martin Dorey
Subject: [bug #51974] multiline (define/endef) containing target-specific assignments causes errors in /bin/sh
Date: Sat, 9 Sep 2017 20:23:09 -0400 (EDT)
User-agent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/58.0.3029.81 Safari/537.36

Follow-up Comment #4, bug #51974 (project make):

I can't dispute Anonymous's advice, which was what I first thought of too, but
I don't think it's clearly documented, neither in the GNU make manual nor in
this vein of bugs, how makefile fragments like these are being parsed. 
Perhaps this example will help explain what was going on in the other cases:

address@hidden:~/tmp/make-51972$ cat case-6.make 
define MACRO
A: B

(The pointlessness of $(call) with no arguments is documented.)

Look away now if you want to guess the behavior on "make -f

address@hidden:~/tmp/make-51972$ make -f case-6.make 
make: *** No rule to make target 'B
hello', needed by 'A'.  Stop.

The result of the variable expansion clearly is being parsed as makefile
syntax, in that it has defined a rule (one without a recipe), but the line
breaks aren't being treated how they would be in a makefile fragment.  Is that
reasonable?  I'll buy it.  But is it obvious?


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