Re: [PATCH 02/16] mescc: Add r0-cmp-r1 instruction.

[Jan Nieuwenhuizen]

W. J. van der Laan writes:

Hello,

> * module/mescc/compile.scm: Make use of a new r0-cmp-r1 instruction.
> This instruction is used to compare two registers and set the flags
> accordingly. In current architectures this is the same as r0-r1, but for
> RISCV it will be different. RISC-V does not have condition flags so
> (until a better solution) we are going to emulate them there.
> * module/mescc/armv4/as.scm: Add r0-cmp-r1 as alias of r0-r1.
> * module/mescc/i386/as.scm: Same.
> * module/mescc/x86_64/as.scm: Same.

Thanks.  Yes, this makes sense.  I have added copyright lines for your
work and modified the commit log like this

--8<---------------cut here---------------start------------->8---
This instruction is used to compare two registers and set the flags
accordingly. In current architectures this is the same as r0-r1, but for
RISCV it will be different.  RISC-V does not have condition flags so
(until a better solution) we are going to emulate them there.

* module/mescc/armv4/as.scm (armv4:instructions): Add r0-cmp-r1 as alias
of r0-r1.
* module/mescc/i386/as.scm: Same.
* module/mescc/x86_64/as.scm: Same.
* module/mescc/compile.scm (expr->register): Make use of the new
r0-cmp-r1 instruction.
--8<---------------cut here---------------end--------------->8---

and applied it to wip-riscv.  Our intention is to finish and merge
wip-m2 for the full source bootstrap as mes-0.24, and then rebase
wip-riscv onto that.

Greetings,
Janneke

-- 
Jan Nieuwenhuizen <janneke@gnu.org> | GNU LilyPond http://lilypond.org
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