Re: justification after @center

[Akim Demaille]

 > Akim Demaille:
 >> This is centered.
 >> This is so incorrectly justified! This is so
 >> incorrectly justified!  This is so incorrectly justified! This is so

 > Not anymore. :)  Patch attached.

It works!  Thanks a lot!

--- /home/akim/www/compil/assignments.txt       2004-02-16 12:10:45.000000000 
+0100
+++ assignments.txt     2004-02-17 12:41:34.000000000 +0100
@@ -1,6 +1,6 @@
                      *Nul n'est censé ignorer la loi.*
- Everything exposed in this document is
-expected to be known.
+
+   Everything exposed in this document is expected to be known.
 
 The Tiger Compiler Project
 **************************
@@ -8,7 +8,7 @@
    This document
 (http://www.lrde.epita.fr/~akim/compil/assignments/assignments.html)
 details the various tasks the "Compilation" students must complete.  It was
-last edited on February 13, 2004.
+last edited on February 17, 2004.
 
 Table of Contents
 *****************
@@ -183,10 +183,10 @@
 document,
 
                      *Nul n'est censé ignorer la loi.*
- That is to say everything exposed in this
-document is considered to be known.  If it is written but you didn't know,
-you are wrong.  If it is not written _and_ was not clearly reported in the
-news, I am wrong.
+
+   That is to say everything exposed in this document is considered to be
+known.  If it is written but you didn't know, you are wrong.  If it is not
+written _and_ was not clearly reported in the news, I am wrong.
 
    Basically this document contains three kinds of informations:
 
@@ -2440,8 +2440,8 @@
 ================================
 
         *2006-T0 delivery is Wednesday, February 4th 2004 at noon.*
- This section
-has been updated for EPITA-2006.
+
+This section has been updated for EPITA-2006.
 
 T0 is a weak form of T1: the scanner and the parser are written, but there
 is a set of simplifications:
@@ -2628,8 +2628,8 @@
 ==========================
 
          *2006-T1 delivery is Sunday, February 8th 2004 at noon.*
- This section is
-updated for EPITA-2006.
+
+This section is updated for EPITA-2006.
 
 Scanner and parser are properly running, but the abstract syntax tree is
 not built yet.  Differences with T0 include:
@@ -2892,10 +2892,10 @@
 This section was last updated for EPITA-2006 on 2004-02-12.
 
            *2006-T2 delivery is Sunday, March 7th 2003 at noon.*
- At the end of this
-stage, the compiler can build abstract syntax trees of Tiger programs and
-pretty-print them.  The parser is equipped with error recovery.  The memory
-is properly deallocated on demand.
+
+At the end of this stage, the compiler can build abstract syntax trees of
+Tiger programs and pretty-print them.  The parser is equipped with error
+recovery.  The memory is properly deallocated on demand.
 
 4.4.1 T2 Goals
 --------------
@@ -3450,9 +3450,9 @@
 This section was last updated for EPITA-2005 on 2003-04-08.
 
           *2005-T4 delivery is Friday, April 25th 2003 at noon.*
- At the end of this
-stage, the compiler type checks Tiger programs.  Clear error messages are
-required.
+
+At the end of this stage, the compiler type checks Tiger programs.  Clear
+error messages are required.
 
 4.6.1 T4 Goals
 --------------
@@ -3725,10 +3725,10 @@
 This section was last updated for EPITA-2005 on 2003-06-10.
 
             *2005-T56 delivery is Friday, June 20th, at noon.*
- At the end of this stage
-the compiler translates the AST into the high level intermediate
-representation, HIR for short.  And, of course, all the errors of previous
-stages have been fixed.
+
+At the end of this stage the compiler translates the AST into the high
+level intermediate representation, HIR for short.  And, of course, all the
+errors of previous stages have been fixed.
 
 4.7.1 T5 Goals
 --------------
@@ -4801,9 +4801,9 @@
 This section was last updated for EPITA-2005 on 2003-05-15.
 
             *2005-T56 delivery is Friday, June 20th, at noon.*
- There will be no
-additional code: there is no "holes" to fill, you have to write the whole
-thing.  Consequently, you may start T6 as soon as you want.
+
+There will be no additional code: there is no "holes" to fill, you have to
+write the whole thing.  Consequently, you may start T6 as soon as you want.
 
 At the end of this stage, the compiler produces low level intermediate
 representation: LIR.  LIR is a subset of the HIR: some patterns are
@@ -5530,8 +5530,8 @@
 =============================
 
            *2005-T7 delivery is Friday, July 4th 2003 at noon.*
- This section was last
-updated for EPITA-2004 and EPITA-2005 on 2003-07-02.
+
+This section was last updated for EPITA-2004 and EPITA-2005 on 2003-07-02.
 
 Please note that the *2005-T7 delivery is an option*: there will be no
 grade, and a single upload will be accepted.  The tests from T0 to T7 tests
@@ -5965,8 +5965,8 @@
 ==========================
 
            *2005-T8 delivery is Friday, July 18th 2003 at noon.*
- This section was last
-updated for EPITA-2004 and EPITA-2005 on 2003-07-02.
+
+This section was last updated for EPITA-2004 and EPITA-2005 on 2003-07-02.
 
 4.10.1 T8 Goals
 ---------------
@@ -6468,8 +6468,8 @@
 ============================
 
        *2005-T9 delivery is on Monday, September 8th 2003 at noon.*
- This section
-was last updated for EPITA-2004 and EPITA-2005 on 2003-08-19.
+
+This section was last updated for EPITA-2004 and EPITA-2005 on 2003-08-19.
 
 At the end of this stage, the compiler produces code that is runnable using
 Mipsy.
@@ -6611,15 +6611,18 @@
 
      $ tc -eIs --tempmap-display -I --time-report print-many.tig
      error-->Execution times (seconds)
-     error--> 8: liveness analysis    : 0.01   (   25%)   0      (    0%)   
0.02   (   50%)
-     error--> 8: liveness edges       : 0.01   (   25%)   0      (    0%)   0  
    (    0%)
+     error--> 8: liveness analysis    : 0.02   (   50%)   0      (    0%)   
0.01   (   25%)
+     error--> 8: liveness edges       : 0      (    0%)   0      (    0%)   
0.01   (   25%)
      error--> 9: coalesce             : 0.01   (   25%)   0      (    0%)   
0.01   (   25%)
-     error--> 9: register allocation  : 0      (    0%)   0      (    0%)   
0.01   (   25%)
+     error--> 9: import_nodes         : 0      (    0%)   0      (    0%)   
0.01   (   25%)
+     error--> 9: register allocation  : 0.01   (   25%)   0      (    0%)   0  
    (    0%)
      error-->Cumulated times (seconds)
      error--> 7: inst-display         : 0.04   (  100%)   0      (    0%)   
0.04   (  100%)
-     error--> 8: liveness analysis    : 0.01   (   25%)   0      (    0%)   
0.02   (   50%)
+     error--> 8: liveness analysis    : 0.02   (   50%)   0      (    0%)   
0.01   (   25%)
+     error--> 8: liveness edges       : 0      (    0%)   0      (    0%)   
0.01   (   25%)
      error--> 9: asm-compute          : 0.04   (  100%)   0      (    0%)   
0.04   (  100%)
      error--> 9: coalesce             : 0.01   (   25%)   0      (    0%)   
0.01   (   25%)
+     error--> 9: import_nodes         : 0      (    0%)   0      (    0%)   
0.01   (   25%)
      error--> 9: register allocation  : 0.04   (  100%)   0      (    0%)   
0.04   (  100%)
      error--> rest                    : 0.04   (  100%)   0      (    0%)   
0.04   (  100%)
      error--> TOTAL (seconds)         : 0.04   user,      0      system,    
0.04   wall
@@ -7473,7 +7476,7 @@
      error-->== Copyright (C) 2002-2003, and GNU GPL'd, by Julian Seward.
      error-->== Using valgrind-2.1.0, a program supervision framework for 
x86-linux.
      error-->== Copyright (C) 2000-2003, and GNU GPL'd, by Julian Seward.
-     error-->== Estimated CPU clock rate is 1669 MHz
+     error-->== Estimated CPU clock rate is 1667 MHz
      error-->== For more details, rerun with: -v
      error-->==
      error-->==
@@ -7772,6 +7775,7 @@
 ==================================
 
                           Version 1.1, March 2000
+
      Copyright (C) 2000 Free Software Foundation, Inc.
      59 Temple Place, Suite 330, Boston, MA  02111-1307, USA
 
@@ -8136,8 +8140,8 @@
 A.3 Colophon
 ============
 
-This is version 0.241 of `assignments.texi', last edited on February 13,
-2004, and compiled 16 February 2004, using:
+This is version 0.241 of `assignments.texi', last edited on February 17,
+2004, and compiled 17 February 2004, using:
 
      $ tc --version
      tc (LRDE Tiger Compiler 0.64a)