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Re: [PATCH] Add riscv-sim.exp

From: Kito Cheng
Subject: Re: [PATCH] Add riscv-sim.exp
Date: Tue, 21 Jul 2020 11:11:20 +0800

Hi Jocob:

I signed an FSF copyright assignment for most gnu toolchain projects
many years ago, but I didn't list DejaGNU, so I'll do the paperwork

> Do I correctly infer that this patch works with the sim tool shipped with GDB?
Tested with GDB simulator and qemu, but we use a tricky way to test
with qemu, add a wrapper to qemu to made the interface same as gdb


> Is similar support planned for QEMU and/or Spike?
There is spike supporting in RISC-V fork dejagnu[1], but is'n
contribute by me or SiFive, my plan is ask Embecosm guys to contribute
after this lading, but I am not sure they have sign the copyright
assignment for dejaGNU or not.


> There is some generic QEMU support in Git master in the file
> baseboards/qemu.exp, but its RISC-V section is in a list of other
> platforms QEMU supports where we are currently unsure of the correct
> target patterns.  Could you take a look at those and align them with the
> RISC-V toolchain?

Oh, thanks for telling me this, it seems like a pretty new file in the
DejaGNU , I'll take a look at this.

On Tue, Jul 21, 2020 at 8:25 AM Rob Savoye <> wrote:
> On 7/20/20 5:23 PM, Jacob Bachmeyer wrote:
> >    Do I correctly infer that this patch works with the sim tool shipped
> > with GDB?
>   That's the default instruction set level simulator, often used when
> working hardware is unavailable. QEMU does have riscv support, so the
> new baseboard for generic QEMU support should work too. I haven't tried
> it yet though. I have looked at the new file, it's not that different
> from all the other *-sim.exp files, so should make the next release.
>         - rob -

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